_origen.standard_sub_blocks.arm_debug

Implements the module _origen.standard_sub_blocks in Python and ties together the PyAPI with the Rust backend. Put another way, this is the Python-side controller for the backend-side model/controller.

Classes

• ArmDebug: Controller connecting the origen.blocks.arm_debug.controller.Controller view

• DP: Undocumented.

• JtagDP: Undocumented.

• MemAP: Undocumented.

class _origen.standard_sub_blocks.arm_debug.ArmDebug

Controller connecting the origen.blocks.arm_debug.controller.Controller view with the backend model. The controller here is responsible for instantiating and initializing the ArmDebug model.

add_mem_ap()

model_init()

switch_to_swd()

class _origen.standard_sub_blocks.arm_debug.DP

model_init()

power_up()

verify_powered_up()

verify_register()

write_register()

class _origen.standard_sub_blocks.arm_debug.JtagDP

model_init()

verify_register()

write_register()

class _origen.standard_sub_blocks.arm_debug.MemAP

model_init()

verify_register()

write_register()

Initiates an ArmDebug MemAP write based on the given register (passed in as a BitCollection). Assumes that all posturing has been completed - that is, the bits’ data, overlay status, etc. is current.