Register Helpers

Use the Origen register API to define registers in the normal way, all of the examples are here are based on this register definition:

# **The Long Name of the Reg**
#
# The MCLKDIV register is used to divide down the frequency of the HBOSCCLK input. If the MCLKDIV
# register is set to value "N", then the output (beat) frequency of the clock divider is OSCCLK / (N+1). The
# resulting beats are, in turn, counted by the PTIMER module to control the duration of Flash high-voltage
# operations.
#
# This is just a test that paragraphs work.
add_reg :mclkdiv, 0x0003, :size => 16 do
  # **Oscillator (Hi)** - Firmware FMU clock source selection. (Note that in addition to this firmware-controlled bit, the
  # FMU clock source is also dependent on test and power control discretes).
  #
  # 0 | FMU clock is the externally supplied bus clock ipg_clk
  # 1 | FMU clock is the internal oscillator from the TFS hardblock
  bit 15, :osch, :reset => 1
  # **Mode Ready** - A Synchronized version of the *ftf_mode_ready[1:0]* output from the flash analog hard block.
  # See the TFL3 Hard Block Creation Guide for more details.
  #
  # 0 | Analog voltages have not reached target levels for the specified mode of operation
  # 1 | Analog voltages have reached target levels for the specified mode of operation
  bit 13..12, :mode_rdy, :writable => false
  # **IFR and FW ECC Enable for LDM** - On / off control for UIFR, RIFR, and FW when reading with the MGATE's
  # Load Memory (LDM) instruction. The setting of this bit only makes a difference when reading with LDM, all other
  # MGATE reads from UIFR/RIFR will always have ECC disabled and reads from FW will have ECC enabled.
  #
  # 0 | ECC is disabled for UIFR, RIFR, and FW reads when using the LDM instruction
  # 1 | ECC is enabled for all UIFR, RIFR, and FW reads when using the LDM instruction
  bit 10, :eccen, :reset => 1
  # **MGATE Command Location Code** - A 2-bit code that tells the MGATE where to go for its instruction fetches
  # (location of command definitions). These bits are used to form different MGATE command request IDs from a
  # falling CCIF, one request ID for each of the possible locations of the MGATE executable. If this field is changed,
  # all subsequent command launches (falling CCIF) will execute from the new area. Note that the MGATE also has
  # a reset request ID. The reset request ID always targets the Boot Code and is unaffected by the CMDLOC setting.
  #
  # 00 | Execute from the Beginning of the MGRAM + 256B (the normal location)
  # 01 | Execute from the Beginning of the MGRAM
  # 10 | Execute from the Stack start at the end of MGRAM
  # 11 | Reserved
  bit 9..7, :cmdloc, :reset => :undefined
  # **Clock Divider Bits** - DIV[7:0] must be set to effectively divide HBOSCCLK down to a known beat frequency
  # having acceptable resolution and dynamic range for timing high-voltage operations on the Flash hardblocks
  # during algorithms with timed events. Table 1-50 shows the range of timed events (i.e. pulse widths) that can be
  # achieved with 8-bit and 16-bit PTIMER loads for various input clock frequencies and clock divider settings.
  bit 6..2, :div, :reset => :memory
end

Basic Register Diagram

Here is an example of how to insert a basic register diagram in a document:

## Register Map

% $dut.regs.each do |name, reg|

<%= render "doc_helpers/register.html", reg: reg, preserve_target: true %>

% end

0x3 - The Long Name of the Reg (mclkdiv)

15 14 13 12 11 10 9 8
R osch 0 mode_rdy[1:0] 0 eccen cmdloc[2:0]
W
Reset 1 0 0 0 1 X
7 6 5 4 3 2 1 0
R cmdloc[2:0] div[4:0] 0 0
W
Reset X M

Register Diagram with Descriptions

Set the :descriptions switch to true to include the register and bit descriptions:

## Register Map

% $dut.regs.each do |name, reg|

<%= render "doc_helpers/register.html", reg: reg, preserve_target: true, descriptions: true %>

% end

0x3 - The Long Name of the Reg (mclkdiv)

The MCLKDIV register is used to divide down the frequency of the HBOSCCLK input. If the MCLKDIV register is set to value “N”, then the output (beat) frequency of the clock divider is OSCCLK / (N+1). The resulting beats are, in turn, counted by the PTIMER module to control the duration of Flash high-voltage operations.

This is just a test that paragraphs work.

15 14 13 12 11 10 9 8
R osch 0 mode_rdy[1:0] 0 eccen cmdloc[2:0]
W
Reset 1 0 0 0 1 X
7 6 5 4 3 2 1 0
R cmdloc[2:0] div[4:0] 0 0
W
Reset X M
Bit Description

15

osch

Oscillator (Hi) - Firmware FMU clock source selection. (Note that in addition to this firmware-controlled bit, the FMU clock source is also dependent on test and power control discretes).

0 FMU clock is the externally supplied bus clock ipg_clk
1 FMU clock is the internal oscillator from the TFS hardblock

13-12

mode_rdy[1:0]

Mode Ready - A Synchronized version of the ftf_mode_ready[1:0] output from the flash analog hard block. See the TFL3 Hard Block Creation Guide for more details.

0 Analog voltages have not reached target levels for the specified mode of operation
1 Analog voltages have reached target levels for the specified mode of operation

10

eccen

IFR and FW ECC Enable for LDM - On / off control for UIFR, RIFR, and FW when reading with the MGATE’s Load Memory (LDM) instruction. The setting of this bit only makes a difference when reading with LDM, all other MGATE reads from UIFR/RIFR will always have ECC disabled and reads from FW will have ECC enabled.

0 ECC is disabled for UIFR, RIFR, and FW reads when using the LDM instruction
1 ECC is enabled for all UIFR, RIFR, and FW reads when using the LDM instruction

9-7

cmdloc[2:0]

MGATE Command Location Code - A 2-bit code that tells the MGATE where to go for its instruction fetches (location of command definitions). These bits are used to form different MGATE command request IDs from a falling CCIF, one request ID for each of the possible locations of the MGATE executable. If this field is changed, all subsequent command launches (falling CCIF) will execute from the new area. Note that the MGATE also has a reset request ID. The reset request ID always targets the Boot Code and is unaffected by the CMDLOC setting.

00 Execute from the Beginning of the MGRAM + 256B (the normal location)
01 Execute from the Beginning of the MGRAM
10 Execute from the Stack start at the end of MGRAM
11 Reserved

6-2

div[4:0]

Clock Divider Bits - DIV[7:0] must be set to effectively divide HBOSCCLK down to a known beat frequency having acceptable resolution and dynamic range for timing high-voltage operations on the Flash hardblocks during algorithms with timed events. Table 1-50 shows the range of timed events (i.e. pulse widths) that can be achieved with 8-bit and 16-bit PTIMER loads for various input clock frequencies and clock divider settings.

## Register Map with Current Value

% $dut.regs.each do |name, reg|

<%= render "doc_helpers/register.html", reg: reg, preserve_target: true, descriptions: true , current_value: true%>

% end

Please note that the highlighting only works when the bit values match explicitly. It will not match partial descriptions, e.g. value is 000 and bitfield description is 00.

Additional Test Cases

0x24 - Protection High (proth)

31 30 29 28 27 26 25 24
R fprot7[7:0]
W
Reset FF
23 22 21 20 19 18 17 16
R fprot6[7:0]
W
Reset EE
15 14 13 12 11 10 9 8
R fprot5[7:0]
W
Reset DD
7 6 5 4 3 2 1 0
R fprot4[7:0]
W
Reset 11

0x28 - Protection Low (protl)

31 30 29 28 27 26 25 24
R fprot3[7:0]
W
Reset M
23 22 21 20 19 18 17 16
R fprot2[7:0]
W
Reset M
15 14 13 12 11 10 9 8
R fprot1[7:0]
W
Reset M
7 6 5 4 3 2 1 0
R fprot0[7:0]
W
Reset M

0xF44 - debug_18

31 30 29 28 27 26 25 24
R placeholder[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R placeholder[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R placeholder[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R placeholder[31:0]
W
Reset 0

0xF48 - debug_19

31 30 29 28 27 26 25 24
R mcsr spa...fg3 frc_wrlvl wrc_dis spa...fg2 cswlo cswl[1:0]
W
Reset 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
R int...sel ign...ull per...vrd bdad rx_skip_tap[2:0] mck_dis
W
Reset 0 0 0 0 0 0
15 14 13 12 11 10 9 8
R curr_adj[3:0] en_tpa tpa_mux_sel[4:0]
W
Reset 0 0 0
7 6 5 4 3 2 1 0
R tpa_mux_sel[4:0] cntr_ovrd cntr_ovrd_val[2:0] tx_bd_en spare_cnfg
W
Reset 0 0 0 0 1
Bit Description

31

mcsr

When this bit is set, the controller’s state machines and queues will be reset. Software then needs to clear this bit to allow the controller to function. This bit can only be set when DDR_SDRAM_CFG[MEM_EN] is cleared.

0 Memory controller is not reset.
1 Memory controller is reset.

30

spare_cnfg3

These are spare configuration bits that can be written or read. However, they are not currently used by the controller.

29

frc_wrlvl

This bit can be set to force the controller to start write leveling. This bit will be cleared by hardware after write leveling is complete.

28

wrc_dis

If this bit is cleared and automatic CAS to Preamble is used, then the DDR controller will calculate the write leveling start values for DQS[1:8] based on the CAS to Preamble results and the start value for DQS[0]. If this bit is set, then the automatic calculation of the start value is disabled.

27

spare_cnfg2

These are spare configuration bits that can be written or read. However, they are not currently used by the controller.

26

cswlo

If this bit is set, then the chip select specified by CSWL will be used during write leveling.

25-24

cswl[1:0]

This field represents the chip select that will be used during write leveling if CSWLO is set.

23

int_ref_sel

This can be set to use an internally generated VRef.

0 Default.
1 Use internal VRef.

22

ign_cas_full

21

perf_en_ovrd

This bit can be set to override the perfmon enable to the controller.

0 Use ipm_plus_perfmon_en.
1 Ignore ipm_plus_perfmon_en and collect perfmon events.

20

bdad

If this bit is set, then the bit deskew results will not be averaged across the enabled ranks. Instead, the address determined by DDR_INIT_ADDR will be used for bit deskew.

19-17

rx_skip_tap[2:0]

This field specifies how many taps will be incremented for each sample during RX bit deskew training. Note that this can be used to improve simulation times when validating the DDR controller RX deskew training.

000 Increment 1 tap at a time
001 Increment 2 taps at a time
010 Increment 4 taps at a time
011 Increment 6 taps at a time
100 Increment 8 taps at a time
101 Increment 10 taps at a time
110 Increment 12 taps at a time
111 Increment 14 taps at a time

16

mck_dis

If this bit is set, then the MCK gating during self refresh will be disabled.

15-12

curr_adj[3:0]

This is the value sent to the IOs for the p_gnd_curr_adj[0:1] and n_gnd_curr_adj[0:1]

11

en_tpa

This is the enable for the TPA pin.

10-6

tpa_mux_sel[4:0]

This 4-bit value represents the 4-bit MUX select to the TPA pin for.

5

cntr_ovrd

This bit can be set to override the counter free-list group. It can be used to force a certain group only to be enabled.

4-2

cntr_ovrd_val[2:0]

This is the value that will be overridden to the counter logic if CNTR_OVRD is set. Note that values of 3’b110 and 3’b111 are illegal, and the will prevent the controller from finding an available counter to use.

1

tx_bd_en

This bit can be set to force the transmit bit deskew to be enabled, regardless of the value of SLOW_EN.

0

spare_cnfg

0xF4C - debug_20

31 30 29 28 27 26 25 24
R placeholder[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R placeholder[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R placeholder[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R placeholder[31:0]
W
Reset 0

0xF50 - debug_21

31 30 29 28 27 26 25 24
R placeholder[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R placeholder[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R placeholder[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R placeholder[31:0]
W
Reset 0

0xF54 - debug_22

31 30 29 28 27 26 25 24
R placeholder[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R placeholder[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R placeholder[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R placeholder[31:0]
W
Reset 0

0xF58 - msb0_debug

msb0_debug (msb0_debug.with_msb0)
LSB0 (MSB0) 31 (0) 30 (1) 29 (2) 28 (3) 27 (4) 26 (5) 25 (6) 24 (7)
[LSB0] R placeholder[30:0]
W
Reset 0
LSB0 (MSB0) 23 (8) 22 (9) 21 (10) 20 (11) 19 (12) 18 (13) 17 (14) 16 (15)
[LSB0] R placeholder[30:0]
W
Reset 0
LSB0 (MSB0) 15 (16) 14 (17) 13 (18) 12 (19) 11 (20) 10 (21) 9 (22) 8 (23)
[LSB0] R placeholder[30:0]
W
Reset 0
LSB0 (MSB0) 7 (24) 6 (25) 5 (26) 4 (27) 3 (28) 2 (29) 1 (30) 0 (31)
[LSB0] R placeholder[30:0] single_bit
W
Reset 0 1
Bit Description

31-1 (0-30)

placeholder[30:0] ([0:30])

placeholder field description

0 (31)

single_bit

single bit

0xF5C - lsb0_non_byte_aligned

8
R placeholder[8:0]
W
Reset 0
7 6 5 4 3 2 1 0
R placeholder[8:0]
W
Reset 0

0xF60 - msb0_non_byte_aligned

msb0_non_byte_aligned (msb0_non_byte_aligned.with_msb0)
LSB0 (MSB0) 8 (0)
[LSB0] R placeholder[8:0]
W
Reset 0
LSB0 (MSB0) 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8)
[LSB0] R placeholder[8:0]
W
Reset 0
Bit Description

8-0 (0-8)

placeholder[8:0] ([0:8])

placeholder field description

0xF64 - lsb0_tiny

2 1 0
R placeholder[2:0]
W
Reset 0

0xF68 - msb0_tiny

msb0_tiny (msb0_tiny.with_msb0)
LSB0 (MSB0) 2 (0) 1 (1) 0 (2)
[LSB0] R placeholder[2:0]
W
Reset 0
Bit Description

2-0 (0-2)

placeholder[2:0] ([0:2])

placeholder field description


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