ruby 3.x support
Added options to permit some different init/end states for write_ir and write_dr if desired.
Update write_ir to behave the same for all testers
Moves pin validation to run time. Makes tdo_store_cycle and tdo_strobe accessors.
added alias method :tclk_cycle
Now adds the necessary meta data during a read transaction to enable OrigenSim to resolve the actual read data in the event of a failed register read.
Added tclk_multiple reader
Adds the ability to override the conventional ‘1’ and ‘0’ drive values on the TCK pin via the following new configuration option:
# My V93K timing setup uses 'P' to enable a clock pulse instead of '1' tclk_vals: { on: 'P', off: 0 }
This is primarily added to support a V93K-style timing setup whereby the clk pin on is defined via a wave called ‘P’ or similar, instead of ‘1’.
sub_block instantiation support and flexibility in pin names
bug fix for digsrc digcap overlay (MSB previously lost)
fix overlay bugs introduced with origen_testers >= 0.10.0 < 0.13.2
added support for tester handled overlay added bit masking support for read while write operation
Correction.
Updated to support non-subroutine type overlays if tester supports labels to permit this. Mainly for UltraFLEX non-subroutine overlay support.
Improved pattern comments
Initial open source release for Origen
Added an ‘arm_debug_comment’ option that will be printed in the pattern just before the data is shifted in. Small bugfix for arm_debug_overlays.
Added an additional check-for-not-fixnum during arm-debug overlays. Updated gemspec to use newer version of RGen (was pre48).
patched in the 3 lines of overlay code that was supposed to be updated in the previous patch.
Based on discussion with Corey, updated previously known as options[:overlay] to options[:arm_debug_overlay], this is causing a naming conflict between arm_debug and nexus. This is just a temporary workaround for everyone, in the future this will be reworked.
add addtional overlay options for write_dr method
Added options to enable arm-debug (which tears apart the registers) to correctly use overlays and asserts (from reads).
Rename gem to ‘rgen_jtag’ as there were conflicts with public gem named ‘jtag’. Added code (commented out) to permit using local/unreleased gem. Updated to support rgen_core v2.5.0.pre18.
Updated to be a gem, per rgen 2.4.0 upgrade.
Bug fix: If an application disabled compares on TDO ($tester.ignore_fails($dut.pin(:tdo) do..) then this was not implemented by the JTAG driver and in fact it would actually remove the suspend on that pin that had been set by the application.
Added test case for this and the necessary patch to fix it.
Made the options argument to Driver#read_dr and Driver#read_ir optional as is the case with the equivalent write methods.
Bumped the min RGen version to pick up a fix for an error caused by bit index references to bits that are not present. i.e. on some RGen versions reg[10] where 10 does not exist will raise an error whereas this driver is coded to expect it to return nil.
Added accessor tclk_format
Added tdo_store_cycle JTAG_CONFIG option to permit specifying which vector to store in multi-cycle TCK format.
Added tdo_strobe JTAG_CONFIG option to permit only strobing TDO when TCK is high for when TCK is greater than 1 tester cycle. Options also include when TCK is low and for all cycles of TCK.
Corrected JTAG shift method to use TCK formatting properly.
Added ability to modify TCLK timing format and the # of cycles TCLK spans for cases where TCLK needs to run at a fraction of another clock pin.
Assumes 50% duty cycle.
To use update JTAG_CONFIG in DUT model, e.g.
JTAG_CONFIG = { :tclk_format => :rl, :tclk_multiple => 4 }
Default is tclk_format = :rh and tclk_multiple = 1
Fixed cases of driving/asserting nil values on a pin which latest RGen doesn’t like.
Added release validation (ensure tests pass).
Added integration with a tester supporting JTAG. If the tester model provides read/write_dr/ir methods then these will be deferred to to handle the requested actions.
In short this means that any apps using a JTAG-based protocol can generate protocol aware or bench patterns by simply using a tester model that implements these methods.
Bug fix to remove extra vector in a shift sequence when a full-width register is overlaid.
Added reset method to tap controller. Can pass message as option to read/write_ir/dr methods that gets put as comment in pattern.
Can now accept RGen::Registers::Container instances in place of regular register objects.
Added min/max RGen versions in place of fixed version. This should not have to change for a long time unless a dependency on a future RGen is added.
Overlay bits will now be generated in-line rather than generating sub-routine calls whenever RGen.mode.simulation? is true.
Added tracking of the IR register value and vectors from repeated calls to the write_ir method with the same value will now be inhibited. Originally it was envisaged that higher level wrappers would take care of this but on reflection this is probably not viable since there may be multiple protocols using the same physical JTAG and therefore it is better tracked at the lowest level.
This change means that higher level libraries can pre-fix all of their operations with a write to the IR with the value they need and the JTAG driver will take care of keeping the vectors optimal.
This version depends on RGen >= v2.0.1.dev98.
Major API update and internal simplification. Removed all local tracking of IR and DR registers states, that should be done by higher level wrappers. See here for full details of the new API: http://rgen.freescale.net/jtag
Removed illegal references to global objects ($soc, $tester, etc.) and added check that the parent implements the required pins.
Initial version, extracted from C90TFS NVM app, probably doesn’t work