| File | % covered | Lines | Relevant Lines | Lines covered | Lines missed | Avg. Hits / Line |
|---|---|---|---|---|---|---|
| lib/origen_nexus.rb | 100.0 % | 11 | 7 | 7 | 0 | 18.4 |
| lib/origen_nexus/driver.rb | 93.58 % | 545 | 218 | 204 | 14 | 900.1 |
| lib/origen_nexus/dut.rb | 100.0 % | 85 | 38 | 38 | 0 | 10.1 |
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require 'origen'
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require_relative '../config/application.rb'
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require_relative '../config/environment.rb'
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require 'origen_jtag' # required for runtime dep gems
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module OrigenNexus
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# Returns an instance of the Nexus::Driver
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def nexus
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@nexus ||= Driver.new(self)
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end
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end
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module OrigenNexus
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class Driver
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# Include JTAG driver instance to fall back on (if owner doesn't have)
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include OrigenJTAG
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# Allow for JTAG optionality
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# blank for now
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JTAG_CONFIG = {}
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# Include registers as Nexus has its own registers
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include Origen::Registers
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alias_method :local_jtag, :jtag
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# Returns the underlying JTAG driver. If the owner has its own JTAG driver
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# then this will be returned, otherwise it will be a fall back driver included
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# by the Nexus module.
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def jtag
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owner.respond_to?(:jtag) ? owner.jtag : local_jtag
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end
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# Returns the object that included the Nexus module,
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# should always be the top-level model
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attr_reader :owner
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# OnCE Command Register (OCMD) width in bits
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# OnCE (On-Chip Emulation)
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attr_reader :once_ocmd_width
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# The OnCE Nexus access instruction (NEXUS-ACCESS)
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# OnCE command value to enable Nexus
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attr_reader :once_nexus_access_instr
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# The OnCE bypass instruction (BYPASS)
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# OnCE command value to bypass OnCE
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attr_reader :once_bypass_instr
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# Nexus command width
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# width of commands used in first DR pass to read/write
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# a Nexus register
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attr_reader :nexus_command_width
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attr_reader :cpuscr_reg_width
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attr_reader :once_cpuscr_go_exit_instr
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def initialize(owner, options = {})
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if defined?(owner.class::NEXUS_CONFIG)
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options = owner.class::NEXUS_CONFIG.merge(options)
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end
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# Fallback defaults
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options = {
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tclk_format: :rh, # format of JTAG clock used: ReturnHigh (:rh), ReturnLo (:rl)
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tclk_multiple: 1, # number of cycles for one clock pulse, assumes 50% duty cycle. Uses tester non-return format to spread TCK across multiple cycles.
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# e.g. @tclk_multiple = 2, @tclk_format = :rh, means one cycle with Tck low (non-return), one with Tck high (NR)
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# @tclk_multiple = 4, @tclk_format = :rl, means 2 cycles with Tck high (NR), 2 with Tck low (NR)
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tdo_strobe: :tclk_high, # when using multiple cycles for TCK, which state of TCK to strobe for TDO, :tclk_high or :tclk_low or :tclk_all
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tdo_store_cycle: 0, # store vector cycle within TCK (i.e. when to indicate to tester to store vector within TCK cycle. 0 is first vector, 1 is second, etc.)
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#
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once_ocmd_width: 10, # Width of OnCE OCMD instruction reg in bits
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once_nexus_access_instr: 0b0001111100, # Instruction used to access nexus via OnCE, default: 0x07C.
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once_bypass_instr: 0b0001111111, # Instruction used to bypass OnCE, default: 0x07F.
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once_cpuscr_go_exit_instr: 0b0110010000, # Instruction used to exit debug mode and kick off code execution from desired address.
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nexus_command_width: 8, # Width of Nexus command data regs, default: 8.
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cpuscr_reg_width: 192, # Width of cpuscr reg
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}.merge(options)
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# Define JTAG configs based on Nexus config
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JTAG_CONFIG[:tclk_format] = options[:tclk_format]
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JTAG_CONFIG[:tclk_multiple] = options[:tclk_multiple]
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JTAG_CONFIG[:tdo_strobe] = options[:tdo_strobe]
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JTAG_CONFIG[:tdo_store_cycle] = options[:tdo_store_cycle]
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@once_ocmd_width = options[:once_ocmd_width]
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@once_nexus_access_instr = options[:once_nexus_access_instr]
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@once_bypass_instr = options[:once_bypass_instr]
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@once_cpuscr_go_exit_instr = options[:once_cpuscr_go_exit_instr]
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@nexus_command_width = options[:nexus_command_width]
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@cpuscr_reg_width = options[:cpuscr_reg_width]
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# Define nexus registers
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define_nexus_registers
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# Define CPU registers
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define_cpu_registers
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@owner = owner
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end
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def on_created
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end
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# This proxies all pin requests from our local JTAG driver to
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# our parent DUT model
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def pin(*args)
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owner.pin(*args)
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end
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alias_method :pins, :pin
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# Define Nexus registers
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# For now only those related to RWA will be defined.
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# RWA (read/write access) provides DMA-like access to memory-mapped resources on
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# the AHB system bus either while the processor is halted or during runtime.
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def define_nexus_registers
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# Each register has a Nexus Opcode, which we will use as 'address' below, and
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# corresponding read addresses and write addresses
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# RWCS - Read/Write Access Control Register
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# read addr = 0x0E, write addr = 0x0F
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reg :rwcs, 0x0E, size: 32 do
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bit 31, :ac
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bit 30, :rw
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bit 29..27, :sz
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bit 26..24, :map
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bit 23..22, :pr
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bit 15..2, :cnt
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bit 1, :err, writable: false
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bit 0, :dv, writable: false
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end
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# RWD - Read/Write Access Data
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# read addr = 0x12, write addr = 0x13
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reg :rwa, 0x12, size: 32 do
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bit 31..0, :addr
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end
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# RWD - Read/Write Access Data
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# read addr = 0x14, write addr = 0x15
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reg :rwd, 0x14, size: 32 do
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bit 31..0, :data
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end
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end
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def define_cpu_registers
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reg :cpuscr, 0x0, size: 192 do
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bit 191..160, :ctl
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bit 159..128, :ir
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bit 127..96, :pc
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bit 95..64, :msr
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bit 63..32, :wbbrh
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bit 31..0, :wbbrl
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end
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end
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# Enable Nexus module
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# Loads NEXUS-ACCESS instruction into JTAG Instruction
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# Register (OnCE OCMD register).
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# repeated calls will not generate vectors if the instruction
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# is already loaded
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#
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# Optionally also accepts a block to allow temporary Nexus access
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#
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# nexus.enable_nexus_access do
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# # Do something with nexus enabled
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# end
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# # Nexus access disabled
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#
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def enable_nexus_access
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if @ir_reg_value != once_nexus_access_instr
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jtag.write_ir once_nexus_access_instr, size: once_ocmd_width, msg: log2("Enable Nexus Access: OnCE_Send(#{once_ocmd_width}, 0x%02X)" % [once_nexus_access_instr])
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@ir_reg_value = once_nexus_access_instr
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end
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if block_given?
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yield
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disable_once
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end # whether to mark all bits in RWD for read
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end
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# Disable OnCE
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def disable_once
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if @ir_reg_value != once_bypass_instr
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jtag.write_ir once_bypass_instr, size: once_ocmd_width, msg: log2("Bypass OnCE: OnCE_Send(#{once_ocmd_width}, 0x%02X)" % [once_bypass_instr])
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@ir_reg_value = once_bypass_instr
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end
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end
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def go_exit(code_start_address = 0x4)
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jtag.write_ir once_cpuscr_go_exit_instr, size: once_ocmd_width, msg: log2('Enabling CPUSCR register for read/write access')
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regs(:cpuscr).bit(:wbbrl).write(0x00000000)
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regs(:cpuscr).bit(:wbbrh).write(0x00000000)
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regs(:cpuscr).bit(:msr).write(0x00000000)
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regs(:cpuscr).bit(:pc).write(code_start_address - 4)
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regs(:cpuscr).bit(:ir).write(0x7c0004ac)
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regs(:cpuscr).bit(:ctl).write(0x00000000)
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jtag.write_dr regs(:cpuscr).value, size: cpuscr_reg_width, msg: log2('Writing GO+EXIT to CPUSCR')
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end
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# Write a given Nexus register
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def write_nexus_register(reg_or_val, options = {})
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options = { write: true, # whether to write or read
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overlay: false,
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care_out: false
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}.merge(options)
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addr = exact_address(reg_or_val, options)
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addr += 1 if options[:write] # offset address by 1 since writing
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data = exact_data(reg_or_val, options)
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size = exact_size(reg_or_val, options)
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name = exact_name(reg_or_val, options)
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if options[:write]
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log "Write Nexus Reg: #{name.upcase} at 0x%04X with 0x%08X" % [addr, data]
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else
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log "Read Nexus Reg: #{name.upcase} at 0x%04X with 0x%08X" % [addr, data]
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end
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# first pass : select register via nexus command
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jtag.write_dr addr, size: nexus_command_width, msg: log2("OnCE_Send(#{nexus_command_width}, 0x%02X)" % [addr])
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if options[:overlay] == true
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# if we want to overlay expect values, then
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# put dummy data in vectors to force them to be uncompressable by pattern generator.
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reg_or_val.data = 0x55555555
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data = exact_data(reg_or_val, options)
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end
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if options[:capture]
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reg(reg_or_val.name).store
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end
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if options[:write]
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# second pass : pass data to register
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jtag.write_dr reg_or_val, overlay: options[:overlay], overlay_label: options[:overlay_label], size: size, msg: log2("OnCE_Send(#{size}, 0x%08X)" % [data])
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else
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if options[:care_output]
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reg(reg_or_val.name).read
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end
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# second pass : read data from register
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jtag.read_dr(reg_or_val, overlay: options[:overlay], overlay_label: options[:overlay_label], size: size, msg: log2("OnCE_Read(#{size}, 0x%08X)" % [data]))
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end
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end
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# Read a given Nexus register
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def read_nexus_register(reg_or_val, options = {})
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write_nexus_register(reg_or_val, options.merge(write: false))
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end
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# Write data cycles only for a Register
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# Used if only want data cycles for overlay subroutines
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def write_data_only(reg_or_val, options = {})
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options = { write: true, # whether to write or read
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}.merge(options)
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data = exact_data(reg_or_val, options)
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# Size of RWD register being used for output
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size = reg(:rwd).size
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# if reading a real register then need to handle copying over all data and flags
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# undefined regs will be handled in lower function so that default is to treat
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# as undefined reg (just simple accesses)
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reg(:rwd).overlay(nil) # clear overlay flags if there, as sticky
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if real_reg?(reg_or_val)
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reg(:rwd).copy_all(reg_or_val)
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end
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if options[:write]
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# Send command to write RWD reg
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# Send data value to be written to RWD reg
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reg(:rwd).write(data)
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jtag.shift(reg(:rwd), options.merge(size: size, cycle_last: true, includes_last_bit: true))
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else
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# Mark all bits for read
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reg(:rwd).read
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jtag.shift(reg(:rwd), options.merge(size: size, read: true, cycle_last: true, includes_last_bit: true))
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end
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# Clear flags so as to not affect subsequent reg reads/writes
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reg(:rwd).clear_flags
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reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
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end
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# Read data cycles only for RWD Register
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def read_data_only(reg_or_val, options = {})
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write_data_only(reg_or_val, options.merge(write: false))
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end
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# Single Write to memory-mapped resource
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# for now only supports 32-bit data
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def single_write_access(address, data, options = {})
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options = { write: true, # whether to write or read the register
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undef: true, # whether IPS being accessed is a register or undefined
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count: 1, # by default use single address access mode
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overlay: false, # default: assume not a real register
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nexus_init: true,
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width: 32, # default write width to 32 bits
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}.merge(options)
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if options[:width] == 8
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write_width = 0b0
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elsif options[:width] == 16
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write_width = 0b1
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elsif options[:width] == 32
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write_width = 0b10
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elsif options[:width] == 64
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write_width = 0b11
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else
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Origen.log.warn 'Nexus 3 width supplied is invalid, defaulting to 32 bit width.'
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end
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if options[:nexus_init]
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enable_nexus_access
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end
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# Send command to write RWA reg
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# Send address value to RWA reg
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reg(:rwa).write(address)
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write_nexus_register(reg(:rwa))
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# Send command to write RWCS reg
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# Send settings to RWCS
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reg(:rwcs).bits(:ac).write(1)
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reg(:rwcs).bits(:rw).write(options[:write] ? 1 : 0)
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reg(:rwcs).bits(:sz).write(write_width) # write_width, defaul value = 32 bits.
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reg(:rwcs).bits(:map).write(0b000) # map select = primary
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reg(:rwcs).bits(:pr).write(0b11) # priority = highest
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reg(:rwcs).bits(:cnt).write(options[:count]) # single access
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reg(:rwcs).bits(:err).write(0) # read/write access error
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reg(:rwcs).bits(:dv).write(0) # read/write access data valid
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write_nexus_register(reg(:rwcs))
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if options[:write]
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# Send command to write RWD reg
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# Send data value to be written to RWD reg
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reg(:rwd).write(data)
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write_nexus_register(reg(:rwd), options.reject { |x| x == :address })
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else
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# If undefined reg, then mark all bits for read
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if options[:undef]
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reg(:rwd).read
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end
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# Send command to read RWD reg
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# Read RWD reg value
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reg(:rwd).write(data)
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read_nexus_register(reg(:rwd), options.reject { |x| x == :address })
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end
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end
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# Single Read from memory-mapped resource
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# for now only supports 32-bit data
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def single_read_access(address, data, options = {})
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single_write_access(address, data, options.merge(write: false))
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end
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# Block Write to memory-mapped resources
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# for now only supports 32-bit data
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#
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# address = address at start of block
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# block_data = array of 32-bit values of block data to write
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def block_write_access(address, block_data = [], options = {})
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options = { write: true, # whether to write or read the block
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width: 32 # width default to 32 bits
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}.merge(options)
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block_data.each_index do |i|
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if i == 0 # first do single write access with count > 1
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single_write_access(address, block_data[0], options.merge(count: block_data.count))
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if options[:width] > 32
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8
reg(:rwd).write(block_data[i = i + 1])
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8
if options[:write]
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4
write_nexus_register(reg(:rwd), options)
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else
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read_nexus_register(reg(:rwd), options)
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end
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end
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else
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next if i.odd? && options[:width] > 32
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reg(:rwd).write(block_data[i])
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if options[:write]
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write_nexus_register(reg(:rwd), options)
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else
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read_nexus_register(reg(:rwd), options)
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end
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if options[:width] > 32
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reg(:rwd).write(block_data[i = i + 1])
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8
if options[:write]
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write_nexus_register(reg(:rwd), options)
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else
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4
read_nexus_register(reg(:rwd), options)
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end
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end
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end
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end
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end
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# Block Read of memory-mapped resources
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# for now only supports 32-bit data
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#
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# address = address at start of block
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# block_data = array of 32-bit values of block data to read
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2
def block_read_access(address, block_data = [], options = {})
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block_write_access(address, block_data, options.merge(write: false))
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end
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# def test_read_flag(reg_to_check)
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# reg_to_check.size.times do |i|
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# if reg_to_check.bit(i).is_to_be_read?
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# print "\t\tBIT #{i} of #{reg_to_check.name.upcase} has read flag!\n"
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# else
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# print "\t\tBIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE read flag!\n"
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# end
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# end
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# end
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#
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# def test_store_flag(reg_to_check)
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# reg_to_check.size.times do |i|
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# if reg_to_check.bit(i).is_to_be_stored?
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# print "\t\tBIT #{i} of #{reg_to_check.name.upcase} has store flag!\n"
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# else
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# print "\t\tBIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE store flag!\n"
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# end
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# end
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# end
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#
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# def test_overlay_flag(reg_to_check, options={})
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# options={:msg => ""}.merge(options)
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# reg_to_check.size.times do |i|
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# if reg_to_check.bit(i).has_overlay?
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# print "\t\t#{options[:msg]}: BIT #{i} of #{reg_to_check.name.upcase} has overlay flag!\n"
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# else
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# print "\t\t#{options[:msg]}: BIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE overlay flag!\n"
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# end
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# end
-
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# determines whether real register or not
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2
def real_reg?(reg_or_val)
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1772
reg_or_val.respond_to?(:name)
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end
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-
# Write the given register (or system memory location) or given value to a specified address
-
# reg_or_val := register symbol to use -- assumes register preloaded with
-
# required data to use, can override by using :address option
-
# in which case data to use provided here
-
#
-
# options[:address] := address to write to. This is mandatory in the case of the
-
# reg_or_val argument being a value (for data), if it is a
-
# Register object then this is optional and if present then
-
# will override the register's address.
-
#
-
2
def write_register(reg_or_val, options = {})
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60
options = { write: true, # whether to write or read the register
-
overlay: false
-
}.merge(options)
-
60
address = exact_address(reg_or_val, options)
-
60
data = exact_data(reg_or_val, options)
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60
size = exact_size(reg_or_val, options)
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60
name = (exact_name(reg_or_val, options)).upcase
-
-
60
op = options[:write] ? 'Write' : 'Read'
-
-
# Set undefined register flag to override option for simple_write_access below
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60
options[:undef] = !real_reg?(reg_or_val)
-
-
# if reading a real register then need to handle copying over all data and flags
-
# undefined regs will be handled in lower function so that default is to treat
-
# as undefined reg (just simple accesses)
-
60
reg(:rwd).overlay(nil) # clear overlay flags if there, as sticky
-
60
if real_reg?(reg_or_val)
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48
reg(:rwd).copy_all(reg_or_val)
-
end
-
-
60
cc "**************************** NEXUS REGISTER #{op.upcase} BEGIN ****************************"
-
60
cc "- #{op} Register #{name}: addr: 0x%08X, data: 0x%08X\n" % [address, data]
-
60
single_write_access(address, data, options)
-
60
cc "**************************** NEXUS REGISTER #{op.upcase} END ****************************"
-
-
# Clear flags so as to not affect subsequent reg reads/writes
-
60
reg(:rwd).clear_flags
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60
reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
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end
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2
alias_method :write, :write_register
-
-
# Read the given register (or system memory location) or given value from a specified address
-
# reg_or_val := register symbol to use -- assumes register preloaded with
-
# required data to use, can override by using :address option
-
# in which case data to use provided here
-
#
-
# options[:address] := address to read from. This is mandatory in the case of the
-
# reg_or_val argument being a value (for data), if it is a
-
# Register object then this is optional and if present then
-
# will override the register's address.
-
#
-
2
def read_register(reg_or_val, options = {})
-
36
write_register(reg_or_val, options.merge(write: false))
-
end
-
2
alias_method :read, :read_register
-
-
# Provides exact address value either if a defined register is
-
# provided or if an address is provided
-
2
def exact_address(reg_or_val, options = {})
-
408
address = options[:addr] || options[:address]
-
408
unless address
-
# if no address provided as option then use register address
-
396
if real_reg?(reg_or_val) # if real register
-
396
address = reg_or_val.address # use register address
-
else
-
fail "An :address option must be supplied when not providing a register to Nexus!\n"
-
end
-
end
-
408
address
-
end
-
-
# Provides exact data value either if a defined register is
-
# provided or if an address is provided
-
2
def exact_data(reg_or_val, _options = {})
-
# if no data provided as option then use register data
-
424
if real_reg?(reg_or_val) # if real register
-
404
data = reg_or_val.data # use register value
-
else
-
20
data = reg_or_val # use reg_or_val passed as data
-
end
-
424
data
-
end
-
-
# Provide size of register if real register passed--
-
# otherwise indicate number of bits of data value
-
2
def exact_size(reg_or_val, _options = {})
-
408
if real_reg?(reg_or_val) # if real register
-
396
size = reg_or_val.size # use register size
-
else
-
12
size = reg_or_val.to_s(2).size # get number of bits in value
-
end
-
408
size
-
end
-
-
# Provide name of register, if real register passed
-
# otherwise given 'undef' as name
-
2
def exact_name(reg_or_val, _options = {})
-
408
if real_reg?(reg_or_val) # if real register
-
396
name = reg_or_val.name # use register name
-
else
-
12
name = 'undef' # undefined register
-
end
-
408
name
-
end
-
-
2
def log2(msg)
-
1072
"Nexus::Driver - #{msg}"
-
end
-
-
2
def log(msg)
-
348
cc "#{log2(msg)}"
-
end
-
end
-
end
-
2
module OrigenNexus
-
# This is a dummy DUT model that provides an example of how
-
# the Nexus module should be included
-
2
class DUT
-
# Include the Nexus protocol
-
2
include OrigenNexus
-
-
2
include Origen::Callbacks
-
2
include Origen::Pins
-
2
include Origen::Registers
-
-
2
NEXUS_CONFIG = {
-
tclk_format: :rh,
-
tclk_multiple: 1
-
}
-
-
2
def initialize(options = {})
-
16
NEXUS_CONFIG[:tclk_format] = options[:tclk_format] if options[:tclk_format]
-
16
NEXUS_CONFIG[:tclk_multiple] = options[:tclk_multiple] if options[:tclk_multiple]
-
-
# Any DUT that uses Nexus must declare these pins
-
# (or an alias)
-
-
# OnCE Debug Port pins
-
16
add_pin :tclk
-
16
add_pin :tms
-
16
add_pin :tdi
-
16
add_pin :tdo
-
-
# Define dummy register to use to test Nexus
-
# driver for test purposes
-
16
reg :testme32, 0x007a, size: 32 do
-
16
bit 31..16, :portB
-
16
bit 15..8, :portA
-
16
bit 0, :enable
-
end
-
-
16
reg :status32, 0x007b, size: 32 do
-
16
bit 31..16, :fail_vals, writable: false
-
16
bit 0, :error_bit, writable: false
-
end
-
-
16
reg :testme16, 0x007c, size: 16 do
-
16
bit 15..8, :portD
-
16
bit 7..0, :portC
-
end
-
end
-
-
2
def startup(_options)
-
16
$tester.set_timeset('tp0', 60)
-
end
-
-
2
def read_register(reg, options = {})
-
# $tester.dont_compress = true
-
32
nexus.read_register(reg, options)
-
# $tester.dont_compress = false
-
end
-
-
2
def write_register(reg, options = {})
-
# $tester.dont_compress = true
-
16
nexus.write_register(reg, options)
-
# $tester.dont_compress = false
-
end
-
-
2
def tclk_format
-
16
NEXUS_CONFIG[:tclk_format]
-
end
-
-
2
def tclk_multiple
-
16
NEXUS_CONFIG[:tclk_multiple]
-
end
-
end
-
-
# used to test that Nexus will use the host's
-
# JTAG if present
-
2
class DUTWithJTAG
-
2
include OrigenNexus
-
-
# basically if this attribute available then shows that DUTWithJTAG's
-
# JTAG driver was used instead of imported JTAG driver class.
-
2
def jtag
-
1
:used_host_jtag
-
end
-
end
-
end