LinkDemo::TopLevel


Data output register

31 30 29 28 27 26 25 24
R d[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R d[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R d[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R d[31:0]
W
Reset 0

Data input register

31 30 29 28 27 26 25 24
R d[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R d[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R d[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R d[31:0]
W
Reset 0

Data direction register

31 30 29 28 27 26 25 24
R d[31:0]
W
Reset 0
23 22 21 20 19 18 17 16
R d[31:0]
W
Reset 0
15 14 13 12 11 10 9 8
R d[31:0]
W
Reset 0
7 6 5 4 3 2 1 0
R d[31:0]
W
Reset 0