LinkDemo::TopLevel

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  2. adc
Address Name
Address Name
0x4003B000 sc1
0x4003B008 cfg1
0x4003B00C cfg2
0x4003B010 r
0x4003B018 cv
0x4003B020 sc2
0x4003B024 sc3
0x4003B028 ofs
0x4003B02C pg
0x4003B030 mg
0x4003B034 clpd
0x4003B038 clps
0x4003B03C clp4
0x4003B040 clp3
0x4003B044 clp2
0x4003B048 clp1
0x4003B04C clp0
0x4003B054 clmd
0x4003B058 clms
0x4003B05C clm4
0x4003B060 clm3
0x4003B064 clm2
0x4003B068 clm1
0x4003B06C clm0

ADC Status and Control Registers 1

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R coco aien diff adch[4:0]
W
Reset 0 0 0 1F
Bit Description

7

coco

Conversion Complete Flag

0 Conversion is not completed.
1 Conversion is completed.

6

aien

Interrupt Enable

0 Conversion complete interrupt is disabled.
1 Conversion complete interrupt is enabled.

5

diff

Differential Mode Enable

0 Single-ended conversions and input channels are selected.
1 Differential conversions and input channels are selected.

4-0

adch[4:0]

Input channel select

0 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. AD0 is selected as input.
1 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. AD1 is selected as input.
1010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. AD2 is selected as input.
1011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. AD3 is selected as input.
1100100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
1100101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
1101110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
1101111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
1111101000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
1111101001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
1111110010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
1111110011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
10001001100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
10001001101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
10001010110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
10001010111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
10011100010000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
10011100010001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
10011100011010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
10011100011011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
10011101110100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
10011101110101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
10011101111110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
10011101111111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
10101011111000 Reserved.
10101011111001 Reserved.
10101100000010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
10101100000011 When DIFF=0, Bandgap VREF_OUT (single-ended) is selected as input; when DIFF=1, Bandgap VREF_OUT (differential) is selected as input.
10101101011100 Reserved.
10101101011101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
10101101100110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
10101101100111 Module is disabled.

ADC Configuration Register 1

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R adlpc adiv[1:0] adlsmp mode[1:0] adiclk[1:0]
W
Reset 0 0 0 0 0
Bit Description

7

adlpc

Low-Power Configuration

0 Normal power configuration.
1 Low-power configuration. The power is reduced at the expense of maximum clock speed.

6-5

adiv[1:0]

Clock Divide Select

0 The divide ratio is 1 and the clock rate is input clock.
1 The divide ratio is 2 and the clock rate is (input clock)/2.
1010 The divide ratio is 4 and the clock rate is (input clock)/4.
1011 The divide ratio is 8 and the clock rate is (input clock)/8.

4

adlsmp

Sample Time Configuration

0 Short sample time.
1 Long sample time.

3-2

mode[1:0]

Conversion mode selection

0 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2’s complement output.
1 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2’s complement output.
1010 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2’s complement output
1011 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2’s complement output Reserved. Do not set the field to this value.

1-0

adiclk[1:0]

Input Clock Select

0 Bus clock
1 Alternate clock 2 (ALTCLK2) Bus clock divided by 2(BUSCLK/2)
1010 Alternate clock (ALTCLK)
1011 Asynchronous clock (ADACK)

ADC Configuration Register 2

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 0 muxsel adacken adhsc adlsts[1:0]
W
Reset 0 0 0 0
Bit Description

4

muxsel

ADC Mux Select

0 ADxxa channels are selected.
1 ADxxb channels are selected.

3

adacken

Asynchronous Clock Output Enable

0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
1 Asynchronous clock and clock output is enabled regardless of the state of the ADC.

2

adhsc

High-Speed Configuration

0 Normal conversion sequence selected.
1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

1-0

adlsts[1:0]

Long Sample Time Select

0 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
1 12 extra ADCK cycles; 16 ADCK cycles total sample time.
1010 6 extra ADCK cycles; 10 ADCK cycles total sample time.
1011 2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC Data Result Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R d[15:0]
W
Reset 0
7 6 5 4 3 2 1 0
R d[15:0]
W
Reset 0
Bit Description

15-0

d[15:0]

Data result

Compare Value Registers

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R cv[15:0]
W
Reset 0
7 6 5 4 3 2 1 0
R cv[15:0]
W
Reset 0
Bit Description

15-0

cv[15:0]

Compare Value.

Status and Control Register 2

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R adact adtrg acfe acfgt acren dmaen refsel[1:0]
W
Reset 0 0 0 0 0 0 0
Bit Description

7

adact

Conversion Active

0 Conversion not in progress.
1 Conversion in progress.

6

adtrg

Conversion Trigger Select

0 Software trigger selected.
1 Hardware trigger selected.

5

acfe

Compare Function Enable

0 Compare function disabled.
1 Compare function enabled.

4

acfgt

Compare Function Greater Than Enable

0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

3

acren

Compare Function Range Enable

0 Range function disabled. Only CV1 is compared. {27}
1 Range function enabled. Both CV1 and CV2 are compared. {27}

2

dmaen

DMA Enable

0 DMA is disabled.
1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

1-0

refsel[1:0]

Voltage Reference Selection

0 Default voltage reference pin pair, that is, external pins VREFH and VREFL
1 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
1010 Internal bandgap reference and associated ground reference (V BGH and V BGL ). Consult the Chip Configuration information for details specific to this MCU. Reserved
1011 Reserved - Selects default voltage reference (V REFH and V REFL ) pin pair.

Status and Control Register 3

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R cal calf 0 assitrgen adco avge avgs[1:0]
W
Reset 0 0 0 0 0 0 0
Bit Description

7

cal

Calibration

6

calf

Calibration Failed Flag

0 Calibration completed normally.
1 Calibration failed. ADC accuracy specifications are not guaranteed.

4

assitrgen

Assist Trigger Enable

0 Writes to ADCSC1 COCO bit don’t have an affect on ADTRG.
1 Writes to ADCSC1 COCO bit will be reflected into ADTRG register. Note: When ASSITRGEN is set, writes to ADCSC1 are delayed by 1/2 bus cycle to allow ADCSC1 COCO write to be updated in ADTRG register so conversion type can be correctly generated (software if coco write is 1’b0 causing ADTRG to clear or hardware type if coco write is 1’b1.). Note: User must ensure no hardware trigger is generated between the time ADCSC1 COCO bit is written if value of ADTRG will change to guarantee correct conversion type is generated.

3

adco

Continuous Conversion Enable

0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

2

avge

Hardware Average Enable

0 Hardware average function disabled.
1 Hardware average function enabled.

1-0

avgs[1:0]

Hardware Average Select

0 4 samples averaged.
1 8 samples averaged.
1010 16 samples averaged.
1011 32 samples averaged.

ADC Offset Correction Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R ofs[15:0]
W
Reset 0
7 6 5 4 3 2 1 0
R ofs[15:0]
W
Reset 4
Bit Description

15-0

ofs[15:0]

Offset Error Correction Value

ADC Plus-Side Gain Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R pg[15:0]
W
Reset 82
7 6 5 4 3 2 1 0
R pg[15:0]
W
Reset 0
Bit Description

15-0

pg[15:0]

Plus-Side Gain

ADC Minus-Side Gain Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R mg[15:0]
W
Reset 82
7 6 5 4 3 2 1 0
R mg[15:0]
W
Reset 0
Bit Description

15-0

mg[15:0]

Minus-Side Gain

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clpd[5:0]
W
Reset A
Bit Description

5-0

clpd[5:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clps[5:0]
W
Reset 20
Bit Description

5-0

clps[5:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 clp4[9:0]
W
Reset 2
7 6 5 4 3 2 1 0
R clp4[9:0]
W
Reset 0
Bit Description

9-0

clp4[9:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 clp3[8:0]
W
Reset 1
7 6 5 4 3 2 1 0
R clp3[8:0]
W
Reset 0
Bit Description

8-0

clp3[8:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R clp2[7:0]
W
Reset 80
Bit Description

7-0

clp2[7:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 clp1[6:0]
W
Reset 40
Bit Description

6-0

clp1[6:0]

Calibration Value

ADC Plus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clp0[5:0]
W
Reset 20
Bit Description

5-0

clp0[5:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clmd[5:0]
W
Reset A
Bit Description

5-0

clmd[5:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clms[5:0]
W
Reset 20
Bit Description

5-0

clms[5:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 clm4[9:0]
W
Reset 2
7 6 5 4 3 2 1 0
R clm4[9:0]
W
Reset 0
Bit Description

9-0

clm4[9:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 clm3[8:0]
W
Reset 1
7 6 5 4 3 2 1 0
R clm3[8:0]
W
Reset 0
Bit Description

8-0

clm3[8:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R clm2[7:0]
W
Reset 80
Bit Description

7-0

clm2[7:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 clm1[6:0]
W
Reset 40
Bit Description

6-0

clm1[6:0]

Calibration Value

ADC Minus-Side General Calibration Value Register

31 30 29 28 27 26 25 24
R 0 0 0 0 0 0 0 0
W
Reset
23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0
W
Reset
15 14 13 12 11 10 9 8
R 0 0 0 0 0 0 0 0
W
Reset
7 6 5 4 3 2 1 0
R 0 0 clm0[5:0]
W
Reset 20
Bit Description

5-0

clm0[5:0]

Calibration Value