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1
module OrigenDebuggers
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# Driver for the Segger J-Link debugger: https://www.segger.com/debug-probes.html
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#
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# For reference here is the complete command list for this debugger. Note that while
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# not recommended any of these can be called directly from an application by using the
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# dw (direct write) method, e.g.
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#
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# $tester.dw "hwinfo"
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# $tester.dw "mem 0x1234, 10"
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#
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# Available commands are:
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# ----------------------
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#
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# f Firmware info
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# h halt
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# g go
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# Sleep Waits the given time (in milliseconds). Syntax: Sleep <delay>
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# s Single step the target chip
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# st Show hardware status
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# hwinfo Show hardware info
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# mem Read memory. Syntax: mem <Addr>, <NumBytes> (hex)
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# mem8 Read 8-bit items. Syntax: mem8 <Addr>, <NumBytes> (hex)
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# mem16 Read 16-bit items. Syntax: mem16 <Addr>, <NumItems> (hex)
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# mem32 Read 32-bit items. Syntax: mem32 <Addr>, <NumItems> (hex)
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# w1 Write 8-bit items. Syntax: w1 <Addr>, <Data> (hex)
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# w2 Write 16-bit items. Syntax: w2 <Addr>, <Data> (hex)
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# w4 Write 32-bit items. Syntax: w4 <Addr>, <Data> (hex)
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# erase Erase internal flash of selected device. Syntax: Erase
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# wm Write test words. Syntax: wm <NumWords>
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# is Identify length of scan chain select register
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# ms Measure length of scan chain. Syntax: ms <Scan chain>
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# mr Measure RTCK react time. Syntax: mr
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# q Quit
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# qc Close JLink connection and quit
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# r Reset target (RESET)
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# rx Reset target (RESET). Syntax: rx <DelayAfterReset>
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# RSetType Set the current reset type. Syntax: RSetType <type>
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# Regs Display contents of registers
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# wreg Write register. Syntax: wreg <RegName>, <Value>
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# moe Shows mode-of-entry, meaning: Reason why CPU is halted
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# SetBP Set breakpoint. Syntax: SetBP <addr> [A/T] [S/H]
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# SetWP Set Watchpoint. Syntax: <Addr> [R/W] [<Data> [<D-Mask>] [A-Mask]]
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# ClrBP Clear breakpoint. Syntax: ClrBP <BP_Handle>
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# ClrWP Clear watchpoint. Syntax: ClrWP <WP_Handle>
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# VCatch Write vector catch. Syntax: VCatch <Value>
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# loadbin Load binary file into target memory.
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# Syntax: loadbin <filename>, <addr>
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# savebin Saves target memory into binary file.
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# Syntax: savebin <filename>, <addr>, <NumBytes>
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# verifybin Verfies if the specified binary is already in the target memory at th
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# e specified address.
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# Syntax: verifybin <filename>, <addr>
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# SetPC Set the PC to specified value. Syntax: SetPC <Addr>
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# le Change to little endian mode
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# be Change to big endian mode
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# log Enables log to file. Syntax: log <filename>
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# unlock Unlocks a device. Syntax: unlock <DeviceName>
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# Type unlock without <DeviceName> to get a list
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# of supported device names.
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# nRESET has to be connected
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# term Test command to visualize printf output from the target device,
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# using DCC (SEGGER DCC handler running on target)
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# ReadAP Reads a CoreSight AP register.
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# Note: First read returns the data of the previous read.
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# An additional read of DP reg 3 is necessary to get the data.
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# ReadDP Reads a CoreSight DP register.
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# Note: For SWD data is returned immediately.
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# For JTAG the data of the previous read is returned.
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# An additional read of DP reg 3 is necessary to get the data.
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# WriteAP Writes a CoreSight AP register.
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# WriteDP Writes a CoreSight DP register.
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# SWDSelect Selects SWD as interface and outputs
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# the JTAG -> SWD swichting sequence.
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# SWDReadAP Reads a CoreSight AP register via SWD.
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# Note: First read returns the data of the previous read.
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# An additional read of DP reg 3 is necessary to get the data.
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# SWDReadDP Reads a CoreSight DP register via SWD.
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# Note: Correct data is returned immediately.
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# SWDWriteAP Writes a CoreSight AP register via SWD.
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# SWDWriteDP Writes a CoreSight DP register via SWD.
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# Device Selects a specific device J-Link shall connect to
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# and performs a reconnect.
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# In most cases explicit selection of the device is not necessary.
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# Selecting a device enables the user to make use of the J-Link
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# flash programming functionality as well as using unlimited
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# breakpoints in flash memory.
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# For some devices explicit device selection is mandatory in order
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# to allow the DLL to perform special handling needed by the device.
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# ExpDevList Exports the device names from the DLL internal
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# device list to a text file
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# Syntax: ExpDevList <Filename>
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# PowerTrace Perform power trace (not supported by all models)
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# Syntax: PowerTrace <LogFile> [<ChannelMask> <RefCountSel>]
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# <LogFile>: File to store power trace data to
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# <ChannelMask>: 32-bit mask to specify what channels shall be enabled
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# <SampleFreq>: Sampling frequency in Hz (0 == max)
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# <RefCountSel>: 0: No reference count
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# 1: Number of bytes transmitted on SWO
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# ---- CP15 ------------
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# rce Read CP15. Syntax: rce <Op1>, <CRn>, <CRm>, <Op2>
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# wce Write CP15. Syntax: wce <Op1>, <CRn>, <CRm>, <Op2>, <Data>
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# ---- ICE -------------
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# Ice Show state of the embedded ice macrocell (ICE breaker)
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# ri Read Ice reg. Syntax: ri <RegIndex>(hex)
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# wi Write Ice reg. Syntax: wi <RegIndex>, <Data>(hex)
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# ---- TRACE -----------
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# TAddBranch TRACE - Add branch instruction to trace buffer. Paras:<Addr>,<BAddr>
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# TAddInst TRACE - Add (non-branch) instruction to trace buffer. Syntax: <Addr>
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# TClear TRACE - Clear buffer
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# TSetSize TRACE - Set Size of trace buffer
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# TSetFormat TRACE - SetFormat
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# TSR TRACE - Show Regions (and analyze trace buffer)
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# TStart TRACE - Start
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# TStop TRACE - Stop
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# ---- SWO -------------
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# SWOSpeed SWO - Show supported speeds
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# SWOStart SWO - Start
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# SWOStop SWO - Stop
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# SWOStat SWO - Display SWO status
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# SWORead SWO - Read and display SWO data
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# SWOShow SWO - Read and analyze SWO data
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# SWOFlush SWO - Flush data
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# SWOView SWO - View terminal data
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# ---- PERIODIC --------
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# PERConf PERIODIC - Configure
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# PERStart PERIODIC - Start
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# PERStop PERIODIC - Stop
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# PERStat PERIODIC - Display status
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# PERRead PERIODIC - Read and display data
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# PERShow PERIODIC - Read and analyze data
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# ---- File I/O --------
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# fwrite Write file to emulator
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# fread Read file from emulator
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# fshow Read and display file from emulator
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# fdelete Delete file on emulator
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# fsize Display size of file on emulator
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# ---- Test ------------
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# TestHaltGo Run go/halt 1000 times
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# TestStep Run step 1000 times
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# TestCSpeed Measure CPU speed.
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# Parameters: [<RAMAddr>]
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# TestWSpeed Measure download speed into target memory.
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# Parameters: [<Addr> [<Size>]]
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# TestRSpeed Measure upload speed from target memory.
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# Parameters: [<Addr> [<Size>] [<NumBlocks>]]
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# TestNWSpeed Measure network download speed.
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# Parameters: [<NumBytes> [<NumReps>]]
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# TestNRSpeed Measure network upload speed.
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# Parameters: [<NumBytes> [<NumReps>]]
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# ---- JTAG ------------
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# Config Set number of IR/DR bits before ARM device.
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# Syntax: Config <IRpre>, <DRpre>
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# speed Set JTAG speed. Syntax: speed <freq>|auto|adaptive, e.g. speed 2000,
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# speed a
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# i Read JTAG Id (Host CPU)
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# wjc Write JTAG command (IR). Syntax: wjc <Data>(hex)
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# wjd Write JTAG data (DR). Syntax: wjd <Data64>(hex), <NumBits>(dec)
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# RTAP Reset TAP Controller using state machine (111110)
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# wjraw Write Raw JTAG data. Syntax: wjraw <NumBits(dec)>, <tms>, <tdi>
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# rt Reset TAP Controller (nTRST)
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# ---- JTAG-Hardware ---
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# c00 Create clock with TDI = TMS = 0
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# c Clock
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# tck0 Clear TCK
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# tck1 Set TCK
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# 0 Clear TDI
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# 1 Set TDI
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# t0 Clear TMS
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# t1 Set TMS
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# trst0 Clear TRST
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# trst1 Set TRST
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# r0 Clear RESET
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# r1 Set RESET
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# ---- Connection ------
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# usb Connect to J-Link via USB. Syntax: usb <port>, where port is 0..3
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# ip Connect to J-Link ARM Pro or J-Link TCP/IP Server via TCP/IP.
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# Syntax: ip <ip_addr>
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# ---- Configuration ---
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# si Select target interface. Syntax: si <Interface>,
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# where 0=JTAG and 1=SWD.
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# power Switch power supply for target. Syntax: power <State> [perm],
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# where State is either On or Off. Example: power on perm
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# wconf Write configuration byte. Syntax: wconf <offset>, <data>
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# rconf Read configuration bytes. Syntax: rconf
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# ipaddr Show/Assign IP address and subnetmask of/to the connected J-Link.
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# gwaddr Show/Assign network gateway address of/to the connected J-Link.
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# dnsaddr Show/Assign network DNS server address of/to the connected J-Link.
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# conf Show configuration of the connected J-Link.
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# ecp Enable the J-Link control panel.
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# calibrate Calibrate the target current measurement.
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# selemu Select a emulator to communicate with,
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# from a list of all emulators which are connected to the host
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# The interfaces to search on, can be specified
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# Syntax: selemu [<Interface0> <Interface1> ...]
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# ShowEmuList Shows a list of all emulators which are connected to the host.
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# The interfaces to search on, can be specified.
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# Syntax: ShowEmuList [<Interface0> <Interface1> ...]
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#
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# ----------------------
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# NOTE: Specifying a filename in command line
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# will start J-Link Commander in script mode.
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1
class JLink < Base
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1
def on_create
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# The minimum time unit is 1ms
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1
set_timeset('default', 1_000_000)
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1
@pat_extension = 'jlk'
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1
@comment_char = '//'
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end
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# All debuggers should try and support these methods
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1
module Common_API
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1
def delay(cycles)
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2
dw "Sleep #{cycles_to_ms(cycles)}"
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end
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1
def write(reg_or_val, options = {})
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3
if reg_or_val.respond_to?(:data)
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2
cc("[JLink] Write #{reg_or_val.name.upcase} register, address: 0x%06X with value: 0x%08X" % [reg_or_val.address, reg_or_val.data])
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end
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3
send("write#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
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end
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1
alias_method :write_register, :write
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1
def read(reg_or_val, options = {})
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7
if reg_or_val.respond_to?(:data)
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4
cc("[JLink] Read #{reg_or_val.name.upcase} register, address: 0x%06X, expect value: 0x%08X" % [reg_or_val.address, reg_or_val.data])
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end
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7
send("read#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
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end
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1
alias_method :read_register, :read
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# Read 8 bits of data to the given byte address
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1
def read8(data, options = {})
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2
read_memory(extract_address(data, options), number: 1)
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end
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1
alias_method :read_byte, :read8
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1
alias_method :read_8, :read8
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# Read 16 bits of data to the given byte address
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1
def read16(data, options = {})
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2
read_memory(extract_address(data, options), number: 2)
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end
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1
alias_method :read_word, :read16
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1
alias_method :read_16, :read16
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# Read 32 bits of data to the given byte address
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#
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# data can be array of registers, if array of data then will auto-incrememnt address
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1
def read32(data, options = {})
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9
options = { optimize: false, # whether to use a single command to do the read
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# user may care regarding endianness
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size: 32, # size of each item in bits
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number: 1, # default number of items
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}.merge(options)
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9
options[:optimize] = options[:optimized] if options[:optimized]
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-
9
if data.is_a?(Array)
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2
if options[:optimize]
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# for optimized option assume single starting address for data in array
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1
read_memory(extract_address(data, options), size: options[:size], number: data.length)
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else
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1
data.each_index do |i|
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4
data_item = data[i]
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# do separate writes for each 32-bit word
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4
read_memory(extract_address(data_item, options) + i * (options[:size] / 8), size: options[:size])
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end
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end
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else
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7
if options[:optimize]
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3
read_memory(extract_address(data, options), size: options[:size], number: options[:number])
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else
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4
read_memory(extract_address(data, options), number: (options[:size] / 8))
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end
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end
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end
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1
alias_method :read_longword, :read32
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1
alias_method :read_32, :read32
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-
# Write 8 bits of data to the given byte address
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1
def write8(data, options = {})
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2
dw "w1 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
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end
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1
alias_method :write_byte, :write8
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1
alias_method :write_8, :write8
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-
# Write 16 bits of data to the given byte address
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1
def write16(data, options = {})
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1
dw "w2 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
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end
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1
alias_method :write_word, :write16
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1
alias_method :write_16, :write16
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-
# Write 32 bits of data to the given byte address
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1
def write32(data, options = {})
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3
dw "w4 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
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end
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1
alias_method :write_longword, :write32
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1
alias_method :write_32, :write32
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-
# @api private
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1
def extract_size(reg_or_val, options = {})
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10
size = options[:size] if options[:size]
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10
unless size
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6
if reg_or_val.respond_to?(:contains_bits?) && reg_or_val.contains_bits?
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6
size = reg_or_val.size
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end
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end
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10
fail 'You must supply an :size option if not providing a register!' unless size
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10
unless [8, 16, 32].include?(size)
-
fail 'Only a size of 8, 16 or 32 is supported!'
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end
-
10
size
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end
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-
# @api private
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1
def extract_data(reg_or_val, options = {})
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6
return options[:data] if options[:data]
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6
return reg_or_val.data if reg_or_val.respond_to?(:data)
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4
reg_or_val
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end
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-
# @api private
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1
def extract_address(reg_or_val, options = {})
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22
addr = options[:addr] || options[:address]
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22
return addr if addr
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6
addr = reg_or_val.address if reg_or_val.respond_to?(:address)
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6
fail 'You must supply an :address option if not providing a register!' unless addr
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6
addr
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end
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end
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1
include Common_API
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-
# If the debugger supports JTAG definitely add these methods, this provides
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# instant compatibility with any application that uses a JTAG based protocol
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1
module JTAG_API
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# Write the given value, register or bit collection to the data register
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1
def write_dr(reg_or_val, options = {})
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2
if reg_or_val.respond_to?(:data)
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1
data = reg_or_val.data
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1
size = options[:size] || reg_or_val.size
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else
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1
data = reg_or_val
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1
size = options[:size]
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end
-
2
dw "wjd 0x#{data.to_s(16).upcase}, #{size}\nc" # the extra clock cycle is needed here to opperate correctly on certain devices
-
# the added clock cycle means that the JLink opperation matches the atp tester opperation (J750 etc)
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# some devices may function without the addition, however an extra clock cycle in "run-Test/idle" is unlikely to
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# break anything so has been added universally.
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end
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-
# Read the given value, register or bit collection from the data register
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1
def read_dr(reg_or_val, options = {})
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# Can't read the DR via J-Link
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end
-
-
# Write the given value, register or bit collection to the instruction register
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1
def write_ir(reg_or_val, options = {})
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2
if reg_or_val.respond_to?(:data)
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1
data = reg_or_val.data
-
else
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1
data = reg_or_val
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end
-
2
dw "wjc 0x#{data.to_s(16).upcase}"
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end
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-
# Read the given value, register or bit collection from the instruction register
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1
def read_ir(reg_or_val, options = {})
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# Can't read the IR via J-Link
-
end
-
end
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1
include JTAG_API
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-
# Other methods can expose unique features of a given debugger
-
1
module Custom
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1
def set_interface(interface)
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# set interface and reset
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value = interface == :swd ? 1 : 0 # set interface : JTAG=0, SWD=1
-
dw "si #{value}"
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# pull a reset now
-
dw 'RSetType 2' # reset via reset pin which should be same as manual reset pin
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# toggle. Also forces CPU to halt when it comes out of reset
-
dw 'r' # reset and halts the device (prob not needed)
-
dw 'halt' # halt core just in case
-
end
-
-
1
def halt
-
dw 'halt'
-
end
-
-
1
def quit
-
dw 'q'
-
end
-
-
1
def read_memory(address, options = {})
-
16
options = {
-
number: 1, # number of items to read
-
size: 8 # number of bits in each item
-
}.merge(options)
-
-
16
if options[:size] == 32
-
8
dw "mem32 0x#{address.to_s(16).upcase}, #{options[:number].to_hex}"
-
8
elsif options[:size] == 16
-
dw "mem16 0x#{address.to_s(16).upcase}, #{options[:number].to_hex}"
-
8
elsif options[:size] == 8
-
8
dw "mem 0x#{address.to_s(16).upcase}, #{options[:number].to_hex}"
-
# not sure difference between mem and mem8
-
else
-
fail 'You must supply a valid :size option!'
-
end
-
end
-
end
-
1
include Custom
-
end
-
end
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1
module OrigenDebuggers
-
# Driver for the P&E Microsystems debugger: https://www.pemicro.com
-
#
-
# For reference here is a command list for this debugger. Note, many commands can be
-
# altered using additional opperands, see help for details. Note that while
-
# not recommended any of these can be called directly from an application by using the
-
# dw (direct write) method, e.g.
-
#
-
# $tester.dw "****"
-
# $tester.dw "****"
-
#
-
# Available commands are:
-
#
-
# write_ir write "raw" jtag to the instruction register
-
# write_dr write "raw" jtag to the data register
-
#
-
# ADDSPR Sets user-defined SPR name to equal user-defined SPR number.
-
# ASCIIF3 (ASCIIF6) Toggle the F3(F6) memory window between showing hexadecimal bytes and ASCII characters. Nonprintable characters are shown as an ASCII period ('.').
-
# ASM Assemble instructions.
-
# BELL Sound Bell
-
# BF Block fill memory.
-
# BGND_TIME Starts processor execution at the current Program Counter and logs time since the last BGND instruction each time a BGND instruction is encountered.
-
# BR Set instruction breakpoint.
-
# CAPTURE Open a capture file named 'filename'.
-
# CAPTUREOFF Turn off capturing and close the current capture file.
-
# CLEARMAP Remove all symbolic mapfile names.
-
# CLEARSYMBOL Remove all temporary symbols.
-
# CLEARVAR Clears variables list from Variables window.
-
# CODE Show disassembled code in the code window starting at address add. If you specify an address in the middle of an intended instruction, improper results may occur.
-
# COLORS Change Debugger Colors
-
# COUNT Counts the number of times breakpoints in internal counter table are executed. Allows optional stop and start parameters to be set.
-
# COUNTER Add or subtract a location from the internal counter table. Using this command with no address shows the current counters.
-
# CR Set Condition Register.
-
# CTR Set Counter Register
-
# DASM Disassemble Instructions
-
# DUMP_TRACE Dump current trace buffer.
-
# DUMP Dumps memory to screen.
-
# EVAL Evaluate expression.
-
# EXECUTE_OPCODE Treats numeric parameter as an opcode and executes it.
-
# EXIT Exit debugger.
-
# FPSCR Set Floating Point Status And Control Register
-
# FR(x) Set Floating Point Register.
-
# G or GO Begin program execution.
-
# GOALL Begin program execution for multi-core devices..
-
# GOEXIT Begin program execution without breakpoints and terminate debugger software.
-
# GOTIL Execute until address.
-
# GOTILROM Execute fast single steps without updating the screen, until the address is reached. This is the fastest way to breakpoint in ROM.
-
# HELP Bring up the help window.
-
# HGO Begin Program Execution
-
# HGOALL Begin Program Execution For Multi-Core Devices
-
# HLOAD Load ELF/DWARF/S19/MAP Object And Debug Information
-
# HLOADMAP Load DWARF/MAP Debug Info Only
-
# HSTEP High-Level Language Source Step
-
# HSTEPALL High-Level Language Source Step For Multi-Core Devices
-
# HSTEPFOR High-Level Language Step Forever
-
# LOADDESK Loads the visual layout for the debugger from the last instance it was saved, such as with the SAVEDESK command.
-
# LOAD_BIN Load a binary file of byte. The default filename extension is .BIN.
-
# LOADV_BIN Perform LOAD_BIN command, verify using the same file.
-
# LOGFILE Open/Close Log File
-
# LR Set Link Register
-
# MACRO Execute a Batch File
-
# MACROEND Stop Saving Commands to File
-
# MACROSTART Save Debug Commands to File
-
# MACS Bring up a window with a list of macros. These are files with the extension .ICD (such as the STARTUP.ICD macro). Use the arrow keys and the <ENTER> key or cancel with the <ESC> key.
-
# MD Set Memory Window 1 to a specific address.
-
# MD2 Set Memory Window 2 to a specific address.
-
# MM Memory modify.
-
# MSR Set Machine Status Register
-
# NOBR Clear all break points.
-
# PC Set Program Counter.
-
# QUIET Turn off (on) refresh of memory based windows.
-
# QUIT Exit debugger.
-
# R Display and edit registers (requires REG software).
-
# R(x) Set General Purpose Register R(x).
-
# REM Place comment in macro file.
-
# RESET Force reset of device into background mode.
-
# RTVAR Displays a specified address and its contents in the Variables window for viewing during code execution and while the part is running (real time).
-
# SAVEDESK Saves the current visual layout of the debugger.
-
# SERIAL Set up parameters for dumb terminal.
-
# SERIALOFF Disable the status window as a dumb terminal.
-
# SERIALON Enable the status window as a dumb terminal.
-
# SHOWCODE Display Code at Address
-
# SHOWMMU Displays MMU Information
-
# SHOWPC Display Code at PC
-
# SHOWSPR Displays SPR Information
-
# SHOWTRACE Allows the user to view this trace buffer after having executed the TRACE command.
-
# SNAPSHOT Send snapshot of screen to capture file.
-
# SOURCEPATH Search for source code.
-
# SPR Display/modify the value of the special purpose register at address add.
-
# SS Execute source step(s)..
-
# ST Execute single step in assembly.
-
# STATUS Show registers.
-
# STEP Same as ST.
-
# STEPALL Execute single step in assembly for multi-core devices.
-
# STEPFOR Step forever on assembly level.
-
# STEPTIL Step until address on the assembly level.
-
# SYMBOL Add user symbol.
-
# TIME Displays real time elapsed during execution of code
-
# _TR Add register field description to the VAR Window
-
# TRACE Monitors execution of the CPU and logs instructions.
-
# UPLOAD_SREC Uloads S records to screen.
-
# VAR Display variable.
-
# VERIFY Compare the contents of program memory with an S-record file.
-
# VERSION Display the version number of the ICD software.
-
# WATCHDOG Disable the watchdog if active.
-
# WHEREIS Display symbol value.
-
# XER Set Integer Exception Register.
-
# ----------------------
-
-
1
class PEmicro < Base
-
1
def on_create
-
3
set_timeset('default', 1_000_000)
-
3
@pat_extension = 'mac'
-
3
@comment_char = ';'
-
3
@in_jtag = false
-
end
-
-
# All debuggers should try and support these methods
-
1
module Common_API
-
1
def delay(cycles)
-
2
dw 'jtag_end' if @in_jtag
-
2
@in_jtag = false
-
2
dw "delay #{cycles_to_ms(cycles)}"
-
end
-
-
1
def write(reg_or_val, options = {})
-
3
dw 'jtag_end' if @in_jtag
-
3
@in_jtag = false
-
3
if reg_or_val.respond_to?(:data)
-
2
cc("[P&E] Write #{reg_or_val.name.upcase} register, address: 0x%06X with value: 0x%08X" % [reg_or_val.address, reg_or_val.data])
-
end
-
3
send("write#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
-
end
-
1
alias_method :write_register, :write
-
-
1
def read(reg_or_val, options = {})
-
7
dw 'jtag_end' if @in_jtag
-
7
@in_jtag = false
-
7
if reg_or_val.respond_to?(:data)
-
4
cc("[P&E] Read #{reg_or_val.name.upcase} register, address: 0x%06X, expect value: 0x%08X" % [reg_or_val.address, reg_or_val.data])
-
end
-
7
send("read#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
-
end
-
1
alias_method :read_register, :read
-
-
# Read 8 bits of data to the given byte address
-
1
def read8(data, options = {})
-
2
dw 'jtag_end' if @in_jtag
-
2
@in_jtag = false
-
2
dw "DUMP.B #{(extract_address(data, options))} #{(extract_address(data, options))}"
-
end
-
1
alias_method :read_byte, :read8
-
1
alias_method :read_8, :read8
-
-
# Read 16 bits of data to the given byte address
-
1
def read16(data, options = {})
-
2
dw 'jtag_end' if @in_jtag
-
2
@in_jtag = false
-
2
dw "DUMP.W #{extract_address(data, options)} #{(extract_address(data, options))}"
-
end
-
1
alias_method :read_word, :read16
-
1
alias_method :read_16, :read16
-
-
# Read 32 bits of data to the given byte address
-
1
def read32(data, options = {})
-
9
dw 'jtag_end' if @in_jtag
-
9
@in_jtag = false
-
9
dw "DUMP.L #{(extract_address(data, options))} #{(extract_address(data, options))}"
-
end
-
1
alias_method :read_longword, :read32
-
1
alias_method :read_32, :read32
-
-
# Write 8 bits of data to the given byte address
-
1
def write8(data, options = {})
-
2
dw 'jtag_end' if @in_jtag
-
2
@in_jtag = false
-
2
dw "MM.B #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
-
end
-
1
alias_method :write_byte, :write8
-
1
alias_method :write_8, :write8
-
-
# Write 16 bits of data to the given byte address
-
1
def write16(data, options = {})
-
1
dw 'jtag_end' if @in_jtag
-
1
@in_jtag = false
-
1
dw "MM.W #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
-
end
-
1
alias_method :write_word, :write16
-
1
alias_method :write_16, :write16
-
-
# Write 32 bits of data to the given byte address
-
1
def write32(data, options = {})
-
3
dw 'jtag_end' if @in_jtag
-
3
@in_jtag = false
-
3
dw "MM.L #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
-
end
-
1
alias_method :write_longword, :write32
-
1
alias_method :write_32, :write32
-
-
# @api private
-
1
def extract_size(reg_or_val, options = {})
-
10
size = options[:size] if options[:size]
-
10
unless size
-
6
if reg_or_val.respond_to?(:contains_bits?) && reg_or_val.contains_bits?
-
6
size = reg_or_val.size
-
end
-
end
-
10
fail 'You must supply an :size option if not providing a register!' unless size
-
10
unless [8, 16, 32].include?(size)
-
fail 'Only a size of 8, 16 or 32 is supported!'
-
end
-
10
size
-
end
-
-
# @api private
-
1
def extract_data(reg_or_val, options = {})
-
6
return options[:data] if options[:data]
-
6
return reg_or_val.data if reg_or_val.respond_to?(:data)
-
4
reg_or_val
-
end
-
-
# @api private
-
1
def extract_address(reg_or_val, options = {})
-
32
addr = options[:addr] || options[:address]
-
32
return addr if addr
-
10
addr = reg_or_val.address if reg_or_val.respond_to?(:address)
-
10
fail 'You must supply an :address option if not providing a register!' unless addr
-
10
addr
-
end
-
end
-
1
include Common_API
-
-
# If the debugger supports JTAG definitely add these methods, this provides
-
# instant compatibility with any application that uses a JTAG based protocol
-
1
module JTAG_API
-
# Write the given value, register or bit collection to the data register
-
1
def write_dr(reg_or_val, options = {})
-
2
dw 'jtag_start' unless @in_jtag
-
2
@in_jtag = true
-
2
if reg_or_val.respond_to?(:data)
-
1
data = reg_or_val.data
-
1
size = options[:size] || reg_or_val.size
-
else
-
1
data = reg_or_val
-
1
size = options[:size]
-
end
-
2
dw "jtag_dr #{size}t #{data.to_s(16).downcase}"
-
end
-
-
# Read the given value, register or bit collection from the data register
-
1
def read_dr(reg_or_val, options = {})
-
# Can't read the DR
-
end
-
-
# Write the given value, register or bit collection to the instruction register
-
1
def write_ir(reg_or_val, options = {})
-
5
dw 'jtag_start' unless @in_jtag
-
5
@in_jtag = true
-
5
size = options[:size] || 4 # Used to be hardcoded to 4 with no override capability
-
5
if reg_or_val.respond_to?(:data)
-
1
data = reg_or_val.data
-
else
-
4
data = reg_or_val
-
end
-
5
dw "jtag_ir #{size}t #{data.to_s(16).downcase}"
-
end
-
-
# Read the given value, register or bit collection from the instruction register
-
1
def read_ir(reg_or_val, options = {})
-
# Can't read the IR
-
end
-
end
-
1
include JTAG_API
-
-
# Other methods can expose unique features of a given debugger
-
1
module Custom
-
1
def set_pc(address)
-
dw 'jtag_end' if @in_jtag
-
@in_jtag = false
-
dw "PC $#{address.to_s(16).upcase}"
-
end
-
1
alias_method :setPC, :set_pc
-
-
1
def go
-
dw 'jtag_end' if @in_jtag
-
@in_jtag = false
-
dw 'GO'
-
end
-
-
1
def halt
-
dw "\n"
-
end
-
-
1
def exit_jtag # not expected to be typically used, should be automatically handled in code, unless manually doing dw "..." calls
-
dw 'jtag_end'
-
@in_jtag = false
-
end
-
-
1
def enter_jtag # not expected to be typically used, should be automatically handled in code, unless manually doing dw "..." calls
-
dw 'jtag_start'
-
@in_jtag = true
-
end
-
end
-
1
include Custom
-
-
1
def footer_template # if at the end of the file, and still in a jtag mode, close the jtag mode.
-
2
if @in_jtag
-
1
"#{Origen.root!}/lib/origen_debuggers/p_e/jtag_end.txt"
-
else
-
1
"#{Origen.root!}/lib/origen_debuggers/p_e/none.txt"
-
end
-
end
-
end
-
end
