Class: OrigenARMDebug::MemAPController

Inherits:
APController show all
Defined in:
lib/origen_arm_debug/mem_ap_controller.rb

Instance Method Summary collapse

Methods inherited from APController

#base_address

Methods included from Helpers

#extract_address, #extract_data, #log

Instance Method Details

#address_increment_enabled? ⇒ Boolean

Returns:

  • (Boolean) 


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# File 'lib/origen_arm_debug/mem_ap_controller.rb', line 62

def address_increment_enabled?
  d = csw.addr_inc.data
  d == 1 || d == 2
end

#read_register(reg_or_val, options = {}) ⇒ Object 



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# File 'lib/origen_arm_debug/mem_ap_controller.rb', line 33

def read_register(reg_or_val, options = {})
  if reg_or_val.try(:owner) == model
    apacc_wait_states = reg_or_val.name == :drw ? (apmem_access_wait + apreg_access_wait) : apreg_access_wait
    log "Read MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{Origen::Utility.read_hex(reg_or_val)}" do
      parent.dp.read_register(reg_or_val, options.merge(apacc_wait_states: apacc_wait_states))
    end

  else

    addr = extract_address(reg_or_val, options)

    log "Read MEM-AP (#{model.name}) address #{addr.to_hex}: #{Origen::Utility.read_hex(reg_or_val)}" do
      csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
      unless tar.data == addr
        tar.write!(addr)
        parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
      end
      drw.reset
      drw.overlay(nil)
      drw.copy_all(reg_or_val)
      parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
      parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
    end
    increment_addr
  end

  reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
end

#write_register(reg_or_val, options = {}) ⇒ Object 



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# File 'lib/origen_arm_debug/mem_ap_controller.rb', line 3

def write_register(reg_or_val, options = {})
  if reg_or_val.try(:owner) == model
    log "Write MEM-AP (#{model.name}) register #{reg_or_val.name.to_s.upcase}: #{reg_or_val.data.to_hex}" do
      parent.dp.write_register(reg_or_val, options)
      apreg_access_wait.cycles
    end
  else

    addr = extract_address(reg_or_val, options)
    data = extract_data(reg_or_val, options)
    ovl = options.delete(:overlay)
    unless ovl.nil?
      Origen.log.warn '[ARM Debug] Overlays only supported through register model'
    end

    log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
      csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
      tar.write!(addr) unless tar.data == addr
      parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
      drw.reset
      drw.overlay(nil)
      drw.copy_all(reg_or_val)
      drw.write!(options)
      latency.cycles
      parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
    end
    increment_addr
  end
end