Class: OrigenARMDebug::MemAP

Inherits:
AP
  • Object
show all
Defined in:
lib/origen_arm_debug/mem_ap.rb

Overview

Memory Access Port (MEM-AP)

Instance Attribute Summary collapse

Attributes inherited from AP

#apreg_access_wait

Instance Method Summary collapse

Constructor Details

#initialize(options = {}) ⇒ MemAP

Returns a new instance of MemAP.



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# File 'lib/origen_arm_debug/mem_ap.rb', line 26

def initialize(options = {})
  super

  @is_axi = options[:is_axi]
  @csw_status_check = options[:csw_status_check]
  @interleave_status_check = options[:interleave_status_check]

  @latency = options[:latency] || 0
  @apmem_access_wait = options[:apmem_access_wait] || 0

  if @is_axi
    reg :csw, 0x0 do |reg|
      reg.bit 31,     :reserved
      reg.bit 30..28, :prot, res: 3
      reg.bit 27..24, :cache
      reg.bit 23,     :spiden
      reg.bit 22..15, :reserved2
      reg.bit 14..13, :domain, res: 3
      reg.bit 12,     :ace_enable
      reg.bit 11..8,  :mode
      reg.bit 7,      :tr_in_prog
      reg.bit 6,      :dbg_status, res: 1
      reg.bit 5..4,   :addr_inc
      reg.bit 3,      :reserved3
      reg.bit 2..0,   :size, res: 2
    end
  else
    reg :csw, 0x0 do |reg|
      reg.bit 31,     :dbg_sw_enable
      reg.bit 30..24, :prot
      reg.bit 23,     :spiden
      reg.bit 11..8,  :mode
      reg.bit 7,      :tr_in_prog
      reg.bit 6,      :device_en
      reg.bit 5..4,   :addr_inc
      reg.bit 2..0,   :size
    end
  end
  reg(:csw).write(options[:csw_reset]) if options[:csw_reset]

  # Doesn't really reset to all 1's, but just to make sure the address
  # optimization logic does not kick in on the first transaction
  add_reg :tar, 0x04, reset: 0xFFFFFFFF
  add_reg :drw, 0x0C, reset: :undefined
  add_reg :bd0, 0x10, reset: :undefined
  add_reg :bd1, 0x14, reset: :undefined
  add_reg :bd2, 0x18, reset: :undefined
  add_reg :bd3, 0x1C, reset: :undefined

  reg :cfg, 0xF4, access: :ro do |reg|
    reg.bit 0, :big_endian
  end

  reg :base, 0xF8, access: :ro do |reg|
    reg.bit 31..12, :baseaddr
    reg.bit 1, :format, reset: 1
    reg.bit 0, :entry_present
  end

  add_reg :idr, 0xFC, access: :ro
end

Instance Attribute Details

#apacc_wait_states ⇒ Object

Wait states to occur in between configuring the DAP for a read, and for the the read transaction to begin.

For JTAG, this is the wait states in between setting the AP and for the read transaction to occur.
For SWD, this is the wait states in between setting the AP, initiating and completing a dummy read, and beginning the actual read transaction.



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# File 'lib/origen_arm_debug/mem_ap.rb', line 15

def apacc_wait_states
  @apacc_wait_states
end

#apmem_access_wait ⇒ Object

Wait states for data to be transferred from Memory Resource to DRW on

read request.  Should be added to apreg_access_wait for complete transaction
time of memory read (read data path: memory->drw->rdbuff)



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# File 'lib/origen_arm_debug/mem_ap.rb', line 10

def apmem_access_wait
  @apmem_access_wait
end

#csw_status_check ⇒ Object

Value to be read from DP CSW for interleaved status checks (debug feature)



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# File 'lib/origen_arm_debug/mem_ap.rb', line 21

def csw_status_check
  @csw_status_check
end

#interleave_status_check ⇒ Object

Boolean value indicating whether to interleave status checks during transactions (debug feature)



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# File 'lib/origen_arm_debug/mem_ap.rb', line 24

def interleave_status_check
  @interleave_status_check
end

#is_axi ⇒ Object

Boolean value indicating whether this is an AXI-AP



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# File 'lib/origen_arm_debug/mem_ap.rb', line 18

def is_axi
  @is_axi
end

#latency ⇒ Object

Latency to write a memory resource



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# File 'lib/origen_arm_debug/mem_ap.rb', line 5

def latency
  @latency
end