Class: OrigenARM::Cores::CortexM::CM33Controller

Inherits:
BaseController show all
Defined in:
lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb

Instance Method Summary collapse

Methods inherited from BaseController

#core_reg_to_dcrdr, #enter_debug_mode_delay!, #exit_debug_mode_delay!, #in_debug_mode, #read_register, #reg_wrapped_by_dcrsr?, #write_register

Constructor Details

#initialize(options = {}) ⇒ CM33Controller

Returns a new instance of CM33Controller



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 6

def initialize(options={})
  super
end

Instance Method Details

#enter_debug_mode(halt_core: true) ⇒ Object

Enters the core's debug mode.

Parameters:

  • halt_core (true, false) —

    Indicates whether the core should be held when entering debug mode. Some functionality may not work correctly if the core is not halted, but a halted core is not a requirement for debug mode.



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 31

def enter_debug_mode(halt_core: true)
  pp('Entering Debug Mode...') do
    reg(:dhcsr).bits(:dbgkey).write(OrigenARM::Cores::CortexM::CM33::Registers::DHCSR_DBGKEY)
    reg(:dhcsr).bits(:c_debugen).write(1)
    reg(:dhcsr).write!
    
    enter_debug_mode_delay!

    if halt_core
      reg(:dhcsr).bits(:dbgkey).write(OrigenARM::Cores::CortexM::CM33::Registers::DHCSR_DBGKEY)
      reg(:dhcsr).bits(:c_debugen).write(1)
      reg(:dhcsr).bits(:c_halt).write(1)
      reg(:dhcsr).write!
      enter_debug_mode_delay!
    end
  end
end

#exit_debug_mode(release_core: true) ⇒ Object

Exits the core's debug mode.

Parameters:

  • release_core (true, false) —

    Indicates whether the core should be held upon exiting debug mode.



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 51

def exit_debug_mode(release_core: true)
  pp('Exiting Debug Mode...') do
    reg(:dhcsr).bits(:dbgkey).write(OrigenARM::Cores::CortexM::CM33::Registers::DHCSR_DBGKEY)
    reg(:dhcsr).bits(:c_halt).write(0) if release_core
    reg(:dhcsr).bits(:c_debugen).write(0)
    reg(:dhcsr).write!
    
    cc 'Delay for the core to exit debug mode'
    exit_debug_mode_delay!
  end
end

#initialize_core(pc:, sp:, release_core: false, sp_lower_limit: nil, sp_upper_limit: nil) ⇒ Object Also known as: initialize_for_lre

TODO:

Implement lower and upper stack pointer limit setting.

Initializes the core, specifically geared towards LRE setup.

Parameters:

  • pc (Fixnum) —

    The absolute address to load into the program counter.

  • sp (Fixnum) —

    The absolute address to load into the current stack pointer.

  • release_core (TrueClass, FalseClass) —

    The core will need to be held in order to initialize. However, this parameter can indicate whether or not the core should be released following the setup.

  • sp_lower_limit (Fixnum) —

    Sets stack pointer's lower limit.

  • sp_upper_limit (Fixnum) —

    Sets stack pointer's upper limit.



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 18

def initialize_core(pc:, sp:, release_core: false, sp_lower_limit: nil, sp_upper_limit: nil)
  enter_debug_mode
  set_sp(sp)
  set_pc(pc)
  # set_stack_limits(sp_lower_limit, sp_upper_limit) if (sp_lower_limit || sp_upper_limit)
  exit_debug_mode(release_core: release_core)
end

#set_pc(pc) ⇒ Object

Note:

This requires the core to be in debug mode, otherwise a bus error will occur.

Note:

This method will also force Thumb mode.

Sets the program counter by writing the debug_return_address register. The debug_return_address will be loaded into the PC following debug mode exit, effectively moving the PC.

Parameters:

  • pc (Fixnum) —

    The new program counter (debug return address).



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 80

def set_pc(pc)
  pp('Patch the Program Counter') do
    # Force the thumb bit. Nothing will work otherwise as CM33 only support THUMB
    reg(:xpsr).bits(:t).write(1)
    reg(:xpsr).write!
    
    # Write the debug return address with the new PC
    # Add 1 to indicate thumb mode
    reg(:debug_return_address).write!(pc + 1)
  end
end

#set_sp(sp) ⇒ Object

Note:

This sets the current stack pointer. The stack pointer in question depends on the core's/device's mode and security settings.

Note:

This requires the core to be in debug mode, otherwise a bus error will occur.

Sets the current stack pointer.

Parameters:

  • sp (Fixnum) —

    The new stack pointer.



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# File 'lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb', line 68

def set_sp(sp)
  pp('Patch the Stack Pointer') do
    reg(:sp).write!(sp)
  end
end