2
          
          require 'origen'
        
      
        

          2
          
          require_relative '../config/application.rb'
        
      
        

          2
          
          require 'origen_testers'
        
      
        

          2
          
          module OrigenAhb
        
      
        

          
          
            # THIS FILE SHOULD ONLY BE USED TO LOAD RUNTIME DEPENDENCIES
        
      
        

          
          
            # If this plugin has any development dependencies (e.g. dummy DUT or other models that are only used
        
      
        

          
          
            # for testing), then these should be loaded from config/boot.rb
        
      
        

          
          
          
        
      
        

          
          
            # Example of how to explicitly require a file
        
      
        

          
          
            # require "origen_ahb/my_file"
        
      
        

          
          
          
        
      
        

          
          
            # Load all files in the lib/origen_ahb directory.
        
      
        

          
          
            # Note that there is no problem from requiring a file twice (Ruby will ignore
        
      
        

          
          
            # the second require), so if you have a file that must be required first, then
        
      
        

          
          
            # explicitly require it up above and then let this take care of the rest.
        
      
        

          2
          
            Dir.glob("#{File.dirname(__FILE__)}/origen_ahb/**/*.rb").sort.each do |file|
        
      
        

          2
          
              require file
        
      
        

          
          
            end
        
      
        

          
          
          
        
      
        

          
          
            # Returns an instance of the OrigenAhb::Driver
        
      
        

          2
          
            def ahb
        
      
        

          1030
          
              @origen_ahb ||= Driver.new(self)
        
      
        

          
          
            end
        
      
        

          
          
          end
        
      
    
  

    

      
        

          2
          
          module OrigenAhb
        
      
        

          2
          
            class Driver
        
      
        

          2
          
              attr_reader :owner
        
      
        

          
          
          
        
      
        

          
          
              # Initialize owner
        
      
        

          2
          
              def initialize(owner, options = {})
        
      
        

          2
          
                @owner = owner
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Read register. Handles register model as input or data/address pair.
        
      
        

          
          
              # Sets up AHB parameters values and passes along to pin-layer ahb
        
      
        

          
          
              # transaction method.
        
      
        

          2
          
              def read_register(reg_or_val, options = {})
        
      
        

          2
          
                options = {
        
      
        

          
          
                  haddr:     options[:address] || reg_or_val.address,
        
      
        

          
          
                  hdata:     reg_or_val,
        
      
        

          
          
                  hwrite:    0,
        
      
        

          
          
                  hsize:     get_hsize(reg_or_val.size),
        
      
        

          
          
                  hburst:    0,
        
      
        

          
          
                  hmastlock: 0,
        
      
        

          
          
                  hprot:     0xF
        
      
        

          
          
                }.merge(options)
        
      
        

          2
          
                cc '==== AHB Read Transaction ===='
        
      
        

          2
          
                if reg_or_val.respond_to?('data')
        
      
        

          1
          
                  data = reg_or_val.data
        
      
        

          1
          
                  name_string = 'Reg: ' + reg_or_val.name.to_s + ' '
        
      
        

          
          
                else
        
      
        

          1
          
                  data = reg_or_val
        
      
        

          1
          
                  options[:hsize] = 2
        
      
        

          1
          
                  name_string = ''
        
      
        

          
          
                end
        
      
        

          2
          
                cc name_string + 'Addr: 0x' + options[:haddr].to_s(16) + ' Data: 0x' + data.to_s(16) + ' Size: ' + options[:hsize].to_s
        
      
        

          2
          
                $dut.ahb_trans(options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Read register. Handles register model as input or data/address pair.
        
      
        

          
          
              # Sets up AHB parameters values and passes along to pin-layer ahb
        
      
        

          
          
              # transaction method.
        
      
        

          2
          
              def write_register(reg_or_val, options = {})
        
      
        

          3
          
                options = {
        
      
        

          
          
                  haddr:     options[:address] || reg_or_val.address,
        
      
        

          
          
                  hdata:     reg_or_val,
        
      
        

          
          
                  hwrite:    1,
        
      
        

          
          
                  hsize:     get_hsize(reg_or_val.size),
        
      
        

          
          
                  hburst:    0,
        
      
        

          
          
                  hmastlock: 0,
        
      
        

          
          
                  hprot:     0xF
        
      
        

          
          
                }.merge(options)
        
      
        

          3
          
                cc '==== AHB Write Transaction ===='
        
      
        

          3
          
                if reg_or_val.respond_to?('data')
        
      
        

          2
          
                  data = reg_or_val.data
        
      
        

          2
          
                  name_string = 'Reg: ' + reg_or_val.name.to_s + ' '
        
      
        

          
          
                else
        
      
        

          1
          
                  data = reg_or_val
        
      
        

          1
          
                  options[:hsize] = 2
        
      
        

          1
          
                  name_string = ''
        
      
        

          
          
                end
        
      
        

          3
          
                cc name_string + 'Addr: 0x' + options[:haddr].to_s(16) + ' Data: 0x' + data.to_s(16) + ' Size: ' + options[:hsize].to_s
        
      
        

          3
          
                $dut.ahb_trans(options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Convert bit width to HSIZE
        
      
        

          2
          
              def get_hsize(size)
        
      
        

          1030
          
                if size <= 8
        
      
        

          11
          
                  hsize = 0
        
      
        

          
          
                elsif size > 8 and size <= 16
        
      
        

          8
          
                  hsize = 1
        
      
        

          
          
                elsif size > 16 and size <= 32
        
      
        

          19
          
                  hsize = 2
        
      
        

          
          
                elsif size > 32 and size <= 64
        
      
        

          32
          
                  hsize = 3
        
      
        

          
          
                elsif size > 64 and size <= 128
        
      
        

          64
          
                  hsize = 4
        
      
        

          
          
                elsif size > 128 and size <= 256
        
      
        

          128
          
                  hsize = 5
        
      
        

          
          
                elsif size > 256 and size <= 512
        
      
        

          256
          
                  hsize = 6
        
      
        

          
          
                elsif size > 512 and size <= 1024
        
      
        

          512
          
                  hsize = 7
        
      
        

          
          
                end
        
      
        

          1030
          
                get_hsize = hsize
        
      
        

          
          
              end
        
      
        

          
          
            end
        
      
        

          
          
          end
        
      
    
  

    

      
        

          2
          
          module OrigenAhbDev
        
      
        

          
          
            # Dummy sub-block for inclusion in top-level dut
        
      
        

          2
          
            class BLOCK
        
      
        

          2
          
              include Origen::Model
        
      
        

          
          
          
        
      
        

          
          
              # Initialize block
        
      
        

          2
          
              def initialize(options = {})
        
      
        

          2
          
                instantiate_registers(options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Create block-level registers
        
      
        

          2
          
              def instantiate_registers(options = {})
        
      
        

          2
          
                add_reg :control, 0x00, 32, data: { pos: 0, bits: 32 }
        
      
        

          2
          
                add_reg :status, 0x04, 32, data: { pos: 0, bits: 32 }
        
      
        

          
          
              end
        
      
        

          
          
            end
        
      
        

          
          
          end
        
      
    
  

    

      
        

          2
          
          module OrigenAhbDev
        
      
        

          
          
            # Top-level chip model for development and unit testing
        
      
        

          2
          
            class DUT
        
      
        

          2
          
              include Origen::TopLevel
        
      
        

          2
          
              include OrigenAhb
        
      
        

          
          
          
        
      
        

          
          
              # Initializer method to setup dut
        
      
        

          2
          
              def initialize(options = {})
        
      
        

          2
          
                instantiate_pins(options)
        
      
        

          2
          
                instantiate_registers(options)
        
      
        

          2
          
                instantiate_sub_blocks(options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Add standard DUT pins and pins necessary for AHB protocol
        
      
        

          2
          
              def instantiate_pins(options = {})
        
      
        

          
          
                # Standard DUT pins
        
      
        

          2
          
                add_pin :tclk
        
      
        

          2
          
                add_pin :tdi
        
      
        

          2
          
                add_pin :tdo
        
      
        

          2
          
                add_pin :tms
        
      
        

          2
          
                add_pin :resetb
        
      
        

          
          
          
        
      
        

          
          
                # AHB Control Signals
        
      
        

          2
          
                add_pin :hclk
        
      
        

          2
          
                add_pin :hready
        
      
        

          2
          
                add_pin :hwrite
        
      
        

          2
          
                add_pin :htrans, size: 2
        
      
        

          2
          
                add_pin :hburst, size: 3
        
      
        

          2
          
                add_pin :hmastlock
        
      
        

          2
          
                add_pin :hsize, size: 3
        
      
        

          2
          
                add_pin :hprot, size: 3
        
      
        

          
          
          
        
      
        

          
          
                # AHB Data Signals
        
      
        

          2
          
                add_pin :haddr, size: 32
        
      
        

          2
          
                add_pin :hwdata, size: 32
        
      
        

          2
          
                add_pin :hrdata, size: 32
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Create a top-level test register
        
      
        

          2
          
              def instantiate_registers(options = {})
        
      
        

          2
          
                add_reg :top_reg, 0x20000000, 32, data: { pos: 0, bits: 32 }
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Create a sub-block for test dut
        
      
        

          2
          
              def instantiate_sub_blocks(options = {})
        
      
        

          2
          
                sub_block :block, class_name: 'OrigenAhbDev::BLOCK', base_address: 0x2200_0000
        
      
        

          
          
              end
        
      
        

          
          
            end
        
      
        

          
          
          end
        
      
    
  

    

      
        

          2
          
          module OrigenAhbDev
        
      
        

          2
          
            class DUTController
        
      
        

          2
          
              include Origen::Controller
        
      
        

          
          
          
        
      
        

          
          
              # Method called on any pattern startup to init timeset and pin values
        
      
        

          2
          
              def startup(options = {})
        
      
        

          1
          
                tester.set_timeset('ahb', 40)
        
      
        

          
          
          
        
      
        

          1
          
                init_pins     # Give pattern a known start up
        
      
        

          
          
          
        
      
        

          
          
                # Do some startup stuff here
        
      
        

          1
          
                pin(:resetb).drive(0)
        
      
        

          1
          
                tester.wait time_in_ns: 250
        
      
        

          1
          
                pin(:resetb).drive(1)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Method called on any pattern shutdown to leave pin values in known state
        
      
        

          2
          
              def shutdown(options = {})
        
      
        

          
          
                # Shut everything down
        
      
        

          1
          
                tester.wait time_in_ns: 250
        
      
        

          1
          
                pin(:resetb).drive(0)
        
      
        

          
          
          
        
      
        

          1
          
                cleanup_pins  # Give patterns a known exit condition
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Set pins to initial pin value
        
      
        

          2
          
              def init_pins
        
      
        

          1
          
                pin(:resetb).drive(0)
        
      
        

          1
          
                pin(:tclk).drive(0)
        
      
        

          1
          
                pin(:tdi).drive(0)
        
      
        

          1
          
                pin(:tms).drive(0)
        
      
        

          1
          
                pin(:tdo).dont_care
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Set pins to safe state for pattern end
        
      
        

          2
          
              def cleanup_pins
        
      
        

          1
          
                pin(:resetb).drive(0)
        
      
        

          1
          
                pin(:tclk).drive(0)
        
      
        

          1
          
                pin(:tdi).drive(0)
        
      
        

          1
          
                pin(:tms).drive(0)
        
      
        

          1
          
                pin(:tdo).dont_care
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Dut-level register write using AHB driver
        
      
        

          2
          
              def write_register(reg_or_val, options = {})
        
      
        

          3
          
                ahb.write_register(reg_or_val, options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Dut-level register read using AHB driver
        
      
        

          2
          
              def read_register(reg_or_val, options = {})
        
      
        

          2
          
                ahb.read_register(reg_or_val, options)
        
      
        

          
          
              end
        
      
        

          
          
          
        
      
        

          
          
              # Pin driver layer of AHB protocol, used by AHB
        
      
        

          2
          
              def ahb_trans(options = {})
        
      
        

          5
          
                pin(:hclk).drive(0)
        
      
        

          5
          
                pins(:htrans).drive(0)
        
      
        

          5
          
                pin(:hwrite).drive(0)
        
      
        

          5
          
                pin(:hsize).drive(0)
        
      
        

          5
          
                pin(:hburst).drive(0)
        
      
        

          5
          
                pin(:hmastlock).drive(0)
        
      
        

          5
          
                pin(:hprot).drive(0)
        
      
        

          5
          
                pin(:hready).dont_care
        
      
        

          5
          
                pins(:haddr).dont_care
        
      
        

          5
          
                pins(:hwdata).dont_care
        
      
        

          5
          
                pins(:hrdata).dont_care
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          
          
                # Address Phase
        
      
        

          
          
                #
        
      
        

          
          
                # Master drives the address and control signals onto bus after the rising edge of HCLK
        
      
        

          5
          
                pin(:hclk).drive(1)
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:htrans).drive(0b00)
        
      
        

          5
          
                pin(:hwrite).drive(options[:hwrite])
        
      
        

          5
          
                pin(:hsize).drive(options[:hsize])
        
      
        

          5
          
                pin(:hburst).drive(options[:hburst])
        
      
        

          5
          
                pin(:hmastlock).drive(options[:hmastlock])
        
      
        

          5
          
                pin(:hprot).drive(options[:hprot])
        
      
        

          5
          
                pins(:haddr).drive(options[:haddr])
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(0)
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          
          
                # Data Phase
        
      
        

          
          
                #
        
      
        

          
          
                # Slave samples the address and control information on the next rising edge of HCLK
        
      
        

          5
          
                pin(:hclk).drive(1)
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(0)
        
      
        

          5
          
                pin(:hready).compare(1)
        
      
        

          5
          
                pins(:hwdata).drive(options[:hdata]) if options[:hwrite] == 1
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(1)
        
      
        

          5
          
                pins(:hrdata).assert(options[:hdata]) if options[:hwrite] == 0
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(0)
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(1)
        
      
        

          5
          
                pins(:htrans).drive(0)
        
      
        

          5
          
                pin(:hwrite).drive(0)
        
      
        

          5
          
                pin(:hsize).drive(0)
        
      
        

          5
          
                pin(:hburst).drive(0)
        
      
        

          5
          
                pin(:hmastlock).drive(0)
        
      
        

          5
          
                pin(:hprot).drive(0)
        
      
        

          5
          
                pin(:hready).dont_care
        
      
        

          5
          
                pins(:haddr).dont_care
        
      
        

          5
          
                pins(:hwdata).dont_care
        
      
        

          5
          
                pins(:hrdata).dont_care
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
          
        
      
        

          5
          
                pin(:hclk).drive(0)
        
      
        

          5
          
                tester.cycle
        
      
        

          
          
              end
        
      
        

          
          
            end
        
      
        

          
          
          end